gbm: move gbm_drm_device::driver_name to gbm_dri_device

The former already keeps track of the DRI module opened, based on the
driver_name provided. So let's keep them together.

As a nice bonus this Will allows us to remove the gbm_drm_device all
together with next patch.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Tested-by: Rob Herring <robh@kernel.org>

gbm: remove "struct gbm_drm_bo" abstraction

The struct is a simple wraper around gbm_bo and brings no actual
benefit.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Tested-by: Rob Herring <robh@kernel.org>

gbm: remove unused gbm_dri_device::loader

Introduced back in 2012 with fd6acb97fb9 ("gbm: Create hooks for
dri2_loader_extension in dri backend") and hasn't been used since.

Seemingly a copy/paste thinko from development stage.

Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Tested-by: Rob Herring <robh@kernel.org>

radv: automake: list shared libraries after the static ones

Analogous to previous commit - the compiler can discard xcb + wayland
libs, since there is no user (the static libraries) before it on the
command line.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>

anv: automake: list shared libraries after the static ones

The compiler can discard the shared ones from the link chain, since
there is no user (the static libraries) before it on the command line.

Cc: mesa-stable@lists.freedesktop.org
Reported-by: Laurent Carlier <lordheavym@gmail.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>

mesa: add KHR_no_error support for glBindImageTextures()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

mesa: add KHR_no_error support for glBindImageTexture()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

mesa: add bind_image_texture() helper

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

mesa: add set_image_binding() helper

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

mesa: remove unused layered parameter from validate_bind_image_texture()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

mesa: add KHR_no_error support for glActiveTexture()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

radeonsi: use ac_build_buffer_load for shader buffer loads

and document why we can't use SMEM yet.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: move building llvm.SI.load.const into ac_build_buffer_load

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: rename readonly_memory -> can_speculate

This is more accurate.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: fix a crash in si_destroy_context if we fail early

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

util: slab_destroy_child should check whether it's been initialized

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radv: Also signal fence if vkAcquireNextImageKHR returns VK_SUBOPTIMAL_KHR.

It is a successful return.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

freedreno: fix fence creation fail if no rendering

Android tries to create a FENCE_FD fence without any rendering.  And
then falls over when that fails.  So just always create an initial
batch.

Fixes: e4ad8695 ("freedreno: fix crash when flush() but no rendering")
Signed-off-by: Rob Clark <robdclark@gmail.com>

radeonsi: drop useless memcmp() check in si_set_blend_color()

cso_set_blend_color() already checks if the old state is different.
Only Nine uses pipe::set_blend_color() directly but I guess it
should use the cache too.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

llvmpipe: add LP_NEW_GS flag for updating vertex info

The vertex information we compute here is really dependent on the last
stage before FS. It just happened to work most of the time because new
GS tend to come with new VS and/or FS...
(The LP_NEW_GS flag was previously set but never used.)

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

svga: document some incorrect VGPU10 shader translation issues

We have a few mistakes in our shader translation code, but the virtual
GPU is forgiving.

Reviewed-by: Michal Krol <michal@vmware.com>
Reviewed-by: Neha Bhende<bhenden@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

i965/copy_image: Use the blitter on gen5

This was just an accidental typo in the refactoring.  The intention was
to try the blitter on gen4-5, not just gen4.

Reviewed-by: Matt Turner <mattst88@gmail.com>

osmesa: link with libunwind if enabled (v2)

Fixes linking error in libOSmesa when using libunwind.

CXXLD    libOSMesa.la
src/gallium/auxiliary/.libs/libgallium.a(u_debug_stack.o): In function `symbol_name_cached':
./src/gallium/auxiliary/util/u_debug_stack.c:87: undefined reference to `_ULx86_64_get_proc_name'
src/gallium/auxiliary/.libs/libgallium.a(u_debug_stack.o): In function `debug_backtrace_capture':
./src/gallium/auxiliary/util/u_debug_stack.c:114: undefined reference to `_Ux86_64_getcontext'
./src/gallium/auxiliary/util/u_debug_stack.c:115: undefined reference to `_ULx86_64_init_local'
./src/gallium/auxiliary/util/u_debug_stack.c:117: undefined reference to `_ULx86_64_step'
./src/gallium/auxiliary/util/u_debug_stack.c:123: undefined reference to `_ULx86_64_get_reg'
./src/gallium/auxiliary/util/u_debug_stack.c:124: undefined reference to `_ULx86_64_get_proc_info'
./src/gallium/auxiliary/util/u_debug_stack.c:120: undefined reference to `_ULx86_64_step'
collect2: error: ld returned 1 exit status

v2 : Fixes title and adds the original error it is fixing.

Signed-off-by: Alexandre Demers <alexandre.f.demers@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

i965/blorp: Support copyteximage on gen4-5

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Use blorp for CopyImageSubData on gen4-5

We keep the blit path because it's probably faster when it works.
However, now that we can use blorp, we can delete that nasty CPU
fall-back path.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Round copy size to the nearest block in intel_miptree_copy

The width and height of the copy don't have to be aligned to the block
size if they specify the right or bottom edges of the image.  (See also
the comment and asserts right above).  We need to round them up when we
do the division in order to get it 100% right.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "17.0 17.1" <mesa-stable@lists.freedesktop.org>

i965: Use BLORP for color clears on gen4-5

We don't support replicated data clears yet.  Those take a bit more work
and enabling replicated data clears in its own commit is probably better
for bisectibility anyway.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Use blorp for color blits on gen4-5

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Assert that no one tries to blit combined depth stencil

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Add blorp support for gen4-5

Due to complications with things such as URB setup on gen4-5, it's
easier to keep gen4 support in blorp completely internal to i965.  This
makes things a bit awkward because that means there's a file in i965
that includes blorp_priv.h but it's either that or have a file in blorp
that includes brw_context.h.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Set additional brw_wm_prog_key fields on gen4-5

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/gen4: Expose the guts of URB recalculation as a helper

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Add support for gen4-5 SF programs

As part of enabling support for SF programs, we plumb the SF URB size
through to emit_urb_config.  For now, it's always zero but, on gen4, it
may be something larger.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Make convert_to_single_slice available outside blorp_blit

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Use designated initializers to set up VERTEX_ELEMENTS

We also add a slot variable and use it as an iterator.  This will make
it much easier to conditionally put something between the header and the
vertex position.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Rename emit_viewport_state to emit_cc_viewport

The real point of this packet is that it sets up CC_VIEWPORT so that
name is a bit better.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Make the common genX_blorp_exec code gen4-safe

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Re-arrange blorp_genX_exec.h

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Don't use ffma directly

It isn't supported prior to gen6 and, on gen6+, NIR will fuse the fmul
and fadd into an ffma automatically for us anyway.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Delete isl_to_gen_ds_surfype

It's no longer used.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Pull the pipeline bits of blorp_exec into a helper

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp/blit: Add support for normalized coordinates

Gen5 and earlier can't do non-normalized coordinates so we need to
compensate in the shader.  Fortunately, it's pretty easy plumb through.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Move clip program compilation to the compiler

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Move SF compilation to the compiler

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/clip: Make brw_clip_prog_key::interp_mode an array

Having it be a pointer means that we end up caching clip programs based
on a pointer to wm_prog_data rather than the actual interpolation modes.
We've been caching one clip program per FS ever since 91d61fbf7cb61a44a
where Timothy rewrote brw_setup_vue_interpolation().

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/sf: make brw_sf_prog_key::interp_mode an array

Having it be a pointer means that we end up caching clip programs based
on a pointer to wm_prog_data rather than the actual interpolation modes.
We've been caching one clip program per FS ever since 91d61fbf7cb61a44a
where Timothy rewrote brw_setup_vue_interpolation().

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/compiler: Make brw_disasm take const assembly

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/decoder: Handle the BLT ring in gen_group_get_length

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

intel/decoder: Handle gen4 VF_STATISTICS and PIPELINE_SELECT

These need special handling because they have no "DWord Length"
parameter and they have an unusual bias of 1.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

intel/genxml: Rename 3DSTATE_AA_LINE_PARAMS on gen5

All of the other gens use "PARAMETERS".

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/genxml: Use the right subtype for VF_STATISTICS on gen4

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/genxml: Iron Lake doesn't support non-normalized sampler coordinates

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/genxml: Add SAMPLER_STATE to gen 4.5

Somehow this got missed.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/genxml: Rename the CC_VIEWPORT pointer on gen4-5

It isn't a pointer to "color calc state", that's the packet it's in.
It's a pointer to the CC viewport state.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/genxml: Sampler state is a pointer on gen4-5

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/genxml: Suffix KSP0 fields on Iron Lake

Iron Lake introduced the multiple KSP thing and so you have KSP0-3.
However, the genxml didn't have an index on the first "Kernel Start
Pointer" or "GRF Register Count".  Add one to match gen6+.  While we're
here, we drop the brackets from the other "GRF Register Count" fields.

Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/genxml: Make a bunch of things offsets on gen4-5

Most things on gen4-5 are addresses because we don't have dynamic state
base address and we don't have instruction state base on gen4.  However,
whoever converted things to addresses got a little over-excited and
converted too much.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/isl: Add gen4_filter_tiling

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/isl: Add support for setting component write disables

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/isl: Add support for gen4 cube maps to get_image_offset_sa

Gen4 cube maps are a 2-D surface with ISL_DIM_LAYOUT_GEN4_3D which is a
bit weird but accurate none the less.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/isl: Don't request space for stencil/hiz packets unless needed

On Iron Lake, the packets exist but we never emit them so there's no
need for us to ask the driver to make batch space for them.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Properly handle mt->first_level

The guts of blorp and ISL don't understand i965's partial miptrees.
Instead, we need to subtract off first_level before we hand anything off
to blorp.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/miptree: Take first_level into account when converting to ISL

ISL doesn't have a concept of a partial miptree.  Instead, we need to
subtract off first_level.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Move the gen7 stencil format workaround to blorp_blit

It's not needed for blorp_copy because it already overrides formats.
It's also not needed for blorp_clear because it clears stencil as
stencil.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Use blorp_copy for doing r8 stencil updates on HSW

The blorp_copy entrypoint is designed for doing memcpy like operations
which is what we need to do here while blorp_blit is for handling format
conversion and scaling.  Using blorp_copy is much simpler and prevents
us from getting formats wrong.  While we're here, we get rid of the
layers_per_blit thing since stencil always uses interleaved MSAA.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Do and end-of-pipe sync on both sides of fast-clear ops

We've discovered in the Vulkan driver that simply doing the end-of-pipe
sync afterwards is insufficient.  The specific requirement stated in the
PRM is that you have to do one every time you transition between the
tree modes of "clear", "render", and "resolve".  This is GL, so we could
track it but any attempt to do so would most likely get it wrong.  For
now, it's easier to just assume that every fast-clear op is an island
and do the sync both before and after.

This also removes the unneeded flush and stall after slow-clear
operations.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Cc: "17.0 17.1" <mesa-stable@lists.freedesktop.org>

amd/common: add missing libdrm include path

Fixes: de9dd4f9f1bb5984c554 ("ac/radeonsi: move struct radeon_info to ac_gpu_info.h")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>

docs: small release calendar fixes

Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>

Revert "amd/common: add vcn dec ip info query"

This reverts commit 524d4fff9e0e58e812e71bc5ba2c92ffa73bee16.

This commit breaks amdgpu on kernels with no DEC IP support.

Caught by the airlied CI system.

Revert "amd/common: set vcn dec as hw decode as well"

This reverts commit 50d322be2f30bb935ee52b3b3649785975771110.

A previous patch breaks amdgpu on non-vcn decode systems,
but have to revert this first.

util: remove unneeded Android ifdef from ralloc.c

SIZE_MAX has been defined in stdint.h on Android since 2013, so this ifdef
is no longer needed.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Rob Herring <robh@kernel.org>

nouveau: drop Android 4.4 and earlier support

Support for Android 4.4 and earlier has already been removed from mesa.
Remove this remaining piece from nouveau, too.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Rob Herring <robh@kernel.org>

i965: use mmap64 for Android

Simplify the handling of mmap for Android by using mmap64 instead. mmap64
may have not existed for Android when this was written, but it's been
around since 2013.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Rob Herring <robh@kernel.org>

gallium/os: use mmap64 for Android

Simplify the handling of mmap for Android by using mmap64 instead. mmap64
may have not existed for Android when this was written, but it's been
around since 2013.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Rob Herring <robh@kernel.org>

Android: generate an error if building on Android 4.4 or earlier

Since commit 7a5b5f52260 ("Android: drop Android 4.4 (KitKat) support"),
Android 4.4 or earlier is no longer supported, so exit with an error if we
try building on it.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Rob Herring <robh@kernel.org>

st/wgl: whitespace, formatting fixes in stw_device.c

Trivial.

glsl: Fix g++ initializer order warning

Fixes this warning:
In file included from ../../../src/compiler/glsl/ir.cpp:25:0:
../../../src/compiler/glsl/ir.h: In constructor 'ir_swizzle::ir_swizzle(ir_rvalue*, ir_swizzle_mask)':
../../../src/compiler/glsl/ir.h:1955:20: warning: 'ir_swizzle::mask' will be initialized after [-Wreorder]
    ir_swizzle_mask mask;
                    ^
../../../src/compiler/glsl/ir.h:1954:15: warning:   'ir_rvalue* ir_swizzle::val' [-Wreorder]
    ir_rvalue *val;
               ^
../../../src/compiler/glsl/ir.cpp:1592:1: warning:   when initialized here [-Wreorder]
 ir_swizzle::ir_swizzle(ir_rvalue *val, ir_swizzle_mask mask)
 ^

Reviewed-by: Matt Turner <mattst88@gmail.com>

radeonsi: enable vcn decode

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

winsys/amdgpu: add vcn dec cs support

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

amd/common: set vcn dec as hw decode as well

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

amd/common: add vcn dec ip info query

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon: rename has_uvd info to has_hw_decode

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/vcn: add decode message for mpeg4 codec

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/vcn: add decode message for mpeg2 codec

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/vcn: add decode message for vc1 codec

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/vcn: add decode message for hevc codec

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/vcn: add decode message decode for avc codec

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/vcn: add decode message feedback

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/vcn: add decode message destroy

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/vcn: add decode message create

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/vcn: add common decode part

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/winsys: add vcn dec ring type

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/winsys: add uvd enc ring type

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/vcn: add vcn decode interface

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

configure.ac: update libdrm amdgpu version requirement to 2.4.81

VCN decode has a new interface, and that depends on the latest libdrm

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

docs: update calendar, add news item and link release notes for 17.1.1

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

docs: add sha256 checksums for 17.1.1

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 092c485b8ed127a15f52434857c37e8021775775)

docs: add release notes for 17.1.1

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit ca0a148a4d09d850f63c82011ac49a311e43e502)

mesa: remove unrequired double calc

type_size() will already handle this correctly for us.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: remove redundant modulus operation

The if check above means we can only get here if size is less than 4.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>