radv: cleanup physical device features

Similar to the physical device properties.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5116>

radv: do not return from radv_GetPhysicalDeviceFeatures2()

This function returns void.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5116>

r600: Use TRUNC_COORD on samplers

As per d573d1d82524b8a2e5f56938069cabc0f0176a0e the same should be done
here. It seems like TRUNCATE_COORD not available on r600, so this is
limited to evergreen.

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5078>

panfrost: Ensure final.no_colour is initialized.

Fix warning reported by Coverity Scan.

Uninitialized scalar variable (UNINIT)
uninit_use: Using uninitialized value final. Field final.no_colour is
uninitialized.

Fixes: 3e4e849e6a96 ("panfrost: Disable tib read/write when colourmask = 0x0")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5183>

r600/sfn: Initialize VertexStageExportForGS m_num_clip_dist member variable.

Fix warning reported by Coverity Scan.

Uninitialized scalar field (UNINIT_CTOR)
uninit_member: Non-static class member m_num_clip_dist is not
initialized in this constructor nor in any functions that it calls.

Fixes: f7df2c57a207 ("r600/sfn: extract class to handle the VS export to different stages")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5180>

llvmpipe: Fix variable name.

Fix warning reported by Coverity Scan.

Unused value (UNUSED_VALUE)
assigned_value: Assigning value from res->nr_samples to
jit_tex->sample_stride here, but that stored value is overwritten before
it can be used.

Fixes: 2e5cddacf7fb ("llvmpipe: add num_samples/sample_stride support to jit textures")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3022
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5179>

docs: drop no-longer-relevant comment about bugzilla

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5172>

tree-wide: fix deprecated GitLab URLs

They will stop working in the next GitLab release, so let's update them
ASAP to make sure things are propagated to everyone by then.

See:
https://about.gitlab.com/releases/2020/05/06/gitlab-com-13-0-breaking-changes/#removal-of-deprecated-project-paths

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5111>

radeonsi/gfx8: enable TC-compatible HTILE from the beginning as before

Fixes: 0d83e7f4b98 - radeonsi: enable TC-compatible HTILE on demand for best Z/S performance
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2921
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2967
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>

radeonsi: don't enable TC-compatible HTILE for stencil if stencil doesn't use it

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>

radeonsi: split si_all_descriptors_begin_new_cs and rename functions

A future commit will extend it.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>

radeonsi: move resetting tracked registers into a new function

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>

ac: update register and packet definitions for preemption

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>

Revert "radeonsi: don't wait for idle at the end of gfx IBs"

This reverts commit 266fec1307b26a544007423582afd8618791893c.

The kernel doesn't wait for idle as part of implicit sync.

Fixes: 266fec1307b26a544007423582afd8618791893c
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2950
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>

radeonsi: decrease the max GS invocation count to 32

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>

radeonsi: don't use INDIRECT_BUFFER within IBs

It's fragile. If I change the size or alignment, it hangs. Better safe than
sorry.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>

ac/surface: don't compute single-sample CMASK if it's unaligned

Displayable DCC can cause this and fail the assertion later.

Fixes: cf61f635ff6a38aad344ebe30551eaaac6fec038
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>

ac/gpu_info: compute the best safe IB alignment

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>

freedreno: Use the right amount of &'s

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5176>

freedreno: Add missing break statement.

Reported-by: Coverity Scan
Fixes: 5a6beb6a24aa ("freedreno: add adreno 650")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5169>

nir/copy_prop_vars: Record progress in more places

Fixes: 96c32d7776 "nir/copy_prop_vars: handle load/store of vector..."
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5170>

nir/opt_deref: Report progress if we remove a deref

Fixes: a1c688517de "nir/opt_deref: Properly optimize ptr_as_array..."
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5170>

nir/lower_double_ops: Rework the if (progress) tree

Fixes: d7d35a9522 "nir/lower_doubles: Use the new NIR lowering..."
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5170>

frontends/va: Fix deinterlace bottom field first flag

Fixes an issue with mpv, where deinterlacing causes the picture to be
offset by one line every other frame in the video.

Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5157>

pan/mdg: Allow DCE on ld_color_buffer masks

Helps with blend shader register pressure.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5153>

pan/mdg: Ensure we don't DCE into impossible masks

We round up for ld/st.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5153>

pan/mdg: Lower shifts to 32-bit

Kind of a hack..

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5153>

pan/mdg: Add pack_colour_32 opcode

Seen for RGB10_A2UI packing.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5153>

panfrost: Handle !independent_blend for blend shaders

Fixes MRT blending.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5153>

panfrost: Use _mesa_roundevenf when packing clear colours

Match blend shader approach.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5153>

panfrost: Fix dated comment

Work register counts are not explicitly stored for blend shaders, and
blend shaders are used for far more than UNORM8.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5153>

Properly check mmap return value

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5150>

ci: Improve baremetal's logging of the job env var passthrough.

Trying to read the sh -x script output was rough, just cat the file once
we're done setting it up.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5089>

ci: Enable a fractional run with UBO-to-constbuf disabled on a3xx.

This gets us coverage of an important case in the HW that the CTS
otherwise basically doesn't hit.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5089>

ci: Don't forget to set NIR_VALIDATE in baremetal runs.

Given that a530 doesn't have cpufreq, we really don't have the time to be
running the validator on all of deqp.  This also helps explain why I had
to go to such a small fraction on the a3xx gles3 run (which we can now
increase).  However, a3xx gles2 seems to be fast enough that we can leave
it enabled and get coverage for older chips.

Because we run more tests now, clear out some stale xfails from the a3xx
list.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5089>

ci: Do an explicit NIR validation-enabled pass on freedreno a630.

We disable it for most of the CTS because it's slow, but let's do a
fractional run to make sure that we don't hit any obvious failures.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5089>

ci: Fix DEQP_CASELIST_FILTER (used by a630 noubo run)

We were doing sed -i /filter/p, which printed everything but printed the
filtered things twice (though they'd only get tested once).  Now that the
filter works, run all the UBO tests instead of doing a 1/5 run, revealing
a new failure.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5089>

gallium/swr: Fix building swr with MSVC

Fix building swr with MSVC by turning off
UNICODE before including windows.h.

Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5166>

mesa: Fix double-lock of Shared->FrameBuffers and usage of wrong mutex

Fixes: 7534c536ca0f4b2b123200f421460094034f37a3
Fixes: 8cfb3e4ee57070ff45e7534a986a20c5fd649dc7
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3024
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5160>

zink: hammer in an explicit wait when retrieving buffer contents for reading

this ensures that the buffer returned is synchronized as expected, though
it incurs a significant performance hit and will hopefully be improved in future
patches

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5120>

zink: reset query on-demand when beginning a new query from resume

the current query pool implementation expects queries to be reset at
the time they're initiated, which means queries started at this point
need to also be explicitly reset

the zink_begin_query() function can't be reused here or else the
query will be double-added to the active list, triggering an infinite loop

ref mesa/mesa#3000

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5120>

zink: fix vkCmdResetQueryPool usage

the final parameter here is the number of queries to reset, not the
index of the last query, meaning that the value passed needs to be
(curr_query + 1) in order to reset the query corresponding to
curr_query

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5120>

zink: flush active queries on destroy and free query object

queries with a valid active_list pointer are likely to still be active,
and vk spec requires them to have completed prior to being destroyed

this isn't completely accurate, as it's currently possible for queries
to remain in the active list while not actually being active, but it
resolves driver crashes that can occur from destroying a stilll-running
query pool object

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5120>

zink: add SpvId returns to a couple ntv functions

this is helpful for debugging

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5120>

zink: explicitly zero some arrays in ntv

just to be safe

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5120>

radeonsi/sdma: remove useless compare

clang warning:
   result of comparison of constant 65536 with expression of type 'uint16_t'
   (aka 'unsigned short') is always true

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5119>

amdgpu: fix unitialized variable

clang warning:
    variable 'va_handle' is used uninitialized whenever 'if' condition is false

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5119>

radeonsi: fix inversed arguments in si_test_gds_memory_management

clang warning:
   implicit conversion from enumeration type 'enum radeon_bo_usage'
   to different enumeration type 'enum radeon_bo_domain'

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5119>

amd/addrlib: fix forgotten char -> enum conversions

clang warning:
  result of comparison of constant 115 with expression of type
  'const enum Dim' is always false

Fixes: e3e704c7e7e ("amd/addrlib: Use enum instead of sparse chars to identify dimensions")
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5119>

glsl: Remove integer matrix support from ir_dereference_array::constant_expression_value

It looks like this code has existed since day 1, but I have no idea why.
There have never been integer matrices in GLSL.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5135>

freedreno/a5xx: Define the 2D blit UBWC pitch fields

Syncing up with my changes to envytools for decoding texturator output.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5127>

freedreno/a5xx: Set MIN_LAYERSZ on 3D textures like we do on a6xx.

These fields (TILE_ALL and MIN_LAYERSZ) seem to be the same on a5xx as
a6xx, having looked at some UBWC vs non-UBWC texturator cases.  Setting
MIN_LAYERSZ does fix the 3D fail we see in the CTS.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5127>

freedreno/a5xx: Add the outline of a unit test for a5xx layout.

Includes a few 3D cases from CTS layouts (since I was looking at CTS
failures) which do justify that a5xx's 3D layout workaround is actually
different from a6xx's.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5127>

freedreno/fdl: Separate the list of a6xx testcases from the the test code.

I'll be reusing the test code for a5xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5127>

freedreno/a5xx: Move resource layout to fdl.

I'm working on fixing the 3D layouts in CI so we can stabilize it, but I
wanted unit tests using the texturator scripts to make sure I don't break
things.  This also makes a5xx and a6xx layout easily comparable again.

This is a straightforward move of the code with prsc references replaced
by arguments in the style of fdl6.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5127>

pan/mdg: Eliminate remaining divisions from compiler

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5154>

pan/mdg: Avoid division in printing helpers

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5154>

pan/mdg: Eliminate 64-bit swizzle packing division

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5154>

pan/mdg: Eliminate expand_writemask division

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5154>

pan/mdg: Cleanup comments that look like division

Don't use a /.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5154>

panfrost: Fix transform feedback types

Don't assume float for everything.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5152>

panfrost: Don't set CAN_DISCARD for MFBD

It's likely harmless but let's match the blob.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>

panfrost: Avoid redundant shader executions with mask=0x0

Only works for a few Midgard GPUs, but hey.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>

panfrost: Disable tib read/write when colourmask = 0x0

There might still be Z/S updates so we can't drop the whole shader but
we can shortcircuit the colour pipeline.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>

panfrost: Remove dated comment about leaks

It's been fixed for a while.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>

panfrost: Limit blend shader work count

To 8, but later we should go much lower.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>

panfrost: Allow tiling on RECT textures

Except for the norm coords bit, they're identical to 2D.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>

panfrost: Allow bpp24 tiling

It's dumb that we have to but it does help RGB8 nontrivially. Alas.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>

panfrost: Don't zero staging buffer for tiling

It's a little less safe but the memset does take time during
initialization. v3d doesn't either, so I think  it's ok.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>

panfrost: Don't set PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY

I'm not aware of any reason this might be necessary, let's avoid the
translate.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>

panfrost: Fill in SCALED formats to format table

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>

panfrost: Remove deadcode

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>

panfrost: Keep cached BOs mmap'd

It doesn't make sense to munmap/mmap repeatedly; they're mapped GPU-side
anyway. So just munmap on free, which will happen in low-mem regardless.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>

panfrost: Guard experimental fp16 behind debug flag

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

pan/mdg: Pack 8-bit swizzles in 16-bit ops

Let's inch closer to 8-bit.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

pan/mdg: Implement condense_writemask for 8-bit

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

pan/mdg: Implement vector constant printing for 8-bit

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

pan/mdg: Use shifts instead of division for RA sizes

We're only dealing with powers-of-two, so this eliminates potential
issues with divisions-by-zero that are otherwise hacked around. Probably
faster too.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

pan/mdg: Pack barriers correctly

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

pan/mdg: Fix type checking issues with compute

SSBO and barriers.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

pan/mdg: Separately pack constants to the upper half

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

pan/mdg: Only combine 16-bit constants to lower half

We can't swizzle both halves simultaneously.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

pan/mdg: Factor out mir_adjust_constant

Each source is semi-independent, we don't need the extra indentation
when the logic is already so complex.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

pan/mdg: Print constant vectors less wrong

For !32-bit types, we need to pay attention to rep_low/high/half to
determine the effective swizzle.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

pan/mdg: Round up bytemasks when spilling

So we can pack the spills for <32-bit types.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

pan/mdg: Print mask when dest=0

Forgot this convention differs from Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

pan/mdg: Set RA bounds for fp16

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

pan/mdg: Eliminate load_64

It can always be inferred from the types.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

pan/mdg: Use type size to determine alignment

Generally, f16 needs to be aligned to 16-bit, f32 to 32-bit, ...

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

pan/lcra: Allow per-variable bounds to be set

Different variables need to respect different bounds. In general,
16-bytes is okay, but for 4-channel 16-bit vectors, we can't cross 8
byte boundaries (else the swizzles will not be packable after), so we
update LCRA to allow this more general form.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

pan/lcra: Remove unused alignment parameters

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

pan/mdg: Ignore dest.type when offseting load swizzle

It's always as-if 32-bit.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

pan/mdg: Don't generate conversions for fp16 LUTs

We can just set the register mode appropriately and then we don't have
to care anywhere else, and there's no extra NIR to chew through. Make
sure we include sqrt too.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

pan/mdg: Implement b2f16

...as iand

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

pan/mdg: Streamline dest_override handling

We can pass it all off to emit time, and let the types in the IR do the
heavylifting in the meantime, which is a lot easier to get right.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

pan/mdg: Remove redundant redundancy

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

pan/mdg: Defer modifier packing until emit time

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

pan/mdg: Remove promote_float pass

Now unused.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

pan/mdg: Promote imov to fmov on a NIR level

Avoids dedicated MIR promote_fmov pass which is unnecessary.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

pan/mdg: Identify scalar integer mods

Symmetric with vector mods, except for normal which is packed as
sign-extend. (flag 2 never seen in the wild)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>