git.libre-soc.org Git - mesa.git/log

radeonsi: clarify the conditions when FLUSH_AND_INV_DB is needed

FLUSH_AND_INV_DB should be done when we're changing surface state
registers of a bound depth target.

When depth_clear_value changes, si_state will modify
S_028038_ZRANGE_PRECISION so we need to flush the DB caches.

Verified with the captures from bugs cited below.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1283
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1330
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4263>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4263>

intel/dump_gpu: Handle a bunch of getparam in the no-HW case

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4250>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4250>

intel/dump_gpu: Add an ensure_device_info helper

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4250>

anv: Stop fetching the timestamp frequency ourselves

gen_get_device_info_from_fd fetches the timestamp frequency from the
kernel. ANV also carrying code for it is redundant.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4250>

egl/android: enable/disable KHR_partial_update correctly

Commit f3728816af (egl/android: require ANDROID_native_fence_sync
for buffer age) re-added some stale code removed in commit
b4345da8762 (egl/android: Delete set_damage_region from egl dri
vtbl). Remove it now.

Commit b4345da8762 assumes KHR_partial_update is only
driver-dependent. That is mostly true except that the extension
also introduces buffer age query, which depends on
ANDROID_native_fence_sync on Android.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Lepton Wu <lepton@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4235>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4235>

ci: Ban the recent popular freedreno a630 intermittent failure.

This popped up last thursday. The only relevant code commit was my pixel
center half integer change, but the more likely thing to me seems to be
having shuffled the test order by introducing more skips the day before.

Link: https://gitlab.freedesktop.org/mesa/mesa/issues/2670
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4287>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4287>

st/mesa: fix use of uninitialized memory due to st_nir_lower_builtin

reported by valgrind

Cc: 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4274>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4274>

aco: fix boolean undef regclass

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4285>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4285>

lima: Add missing source file to Android.mk

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Roman Stratiienko <roman.stratiienko@nure.ua>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4283>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4283>

intel/tools/aubinator_error_decode: Decode ring buffers from HEAD to TAIL

Capture the HEAD and TAIL register values from the dump and
properly index the ring buffer using those. Previously we would
decode the ring buffer from the beginning, printing out whatever
happened to be there.

Also, properly pass the `from_ring` parameter to gen_print_batch()
so that decoding doesn't stop once MI_BATCH_BUFFER_END is
encoutered.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4261>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4261>

docs/features: Update virgl OpenGL 4.5 features
GL_ARB_clip_control and GL_KHR_robustness are now expose in the guest.

Signed-off-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4160>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4160>

intel/tools/aubinator_error_decode: read HW Context before other batches

The hardware context buffer has state that was set before the
batch started. By decoding it first, references to things like
Dynamic State Base Address are decodable in the command batches.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4246>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4246>

iris: Set patch count threshold in 3DSTATE_HS

Lets specifiy maximum number of patches that will be accumulated before
a thread is dispatched.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3563>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3563>

anv: Set patch count threshold in 3DSTATE_HS

Lets specifiy maximum number of patches that will be accumulated before
a thread is dispatched.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3563>

intel/compiler: Track patch count threshold

Return the number of patches to accumulate before an 8_PATCH mode thread
is launched.

v2: (Kenneth Graunke)
- Track patch count threshold instead of input control points.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3563>

intel/genxml: Add patch count threshold field on gen12

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3563>

gitlab-ci/traces: Add Vulkan sample entries for POLARIS10

v2:
- Updated commit log.

Signed-off-by: Andres Gomez <agomez@igalia.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4103>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4103>

gitlab: add bug report template

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4089>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4089>

aco: emit IR in IF's merge block instead if the other side ends in a jump

Fixes NIR such as:
if (divergent) {
   a = sgpr()
} else {
   break;
}
use(a)

Previously we would have emitted:
if (divergent) {
   a = sgpr()
}
if (!divergent) {
   break;
}
use(a)

But "a" isn't available at it's use. Now we emit:
if (divergent) {
}
if (!divergent) {
   break;
}
a = sgpr()
use(a)

pipeline-db (Navi):
Totals from affected shaders:
SGPRS: 1936 -> 1936 (0.00 %)
VGPRS: 1264 -> 1264 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 159408 -> 159152 (-0.16 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 81 -> 81 (0.00 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
CC: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2557
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3658>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3658>

aco: improve check for unreachable loop continue blocks

The old code would have previously caught:
loop {
   ...
   break
}
when it was meant to just catch:
loop {
   if (...)
      break
   else
      break
}

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3658>

aco: skip NIR in unreachable merge blocks

NIR removes most of this but undef instructions for loop header phis can
remain. These were harmless because ACO would DCE them itself.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3658>

aco: handle when ACO adds new continue edges

Usually a loop ends with a uniform continue. If it doesn't and we end up
adding our own continue edges (because of continue_or_break or divergent
breaks at the end), we have to add extra operands to the loop header phis.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3658>

aco: handle missing second predecessors at merge block phis

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3658>

aco: set has_divergent_branch for discards in loops

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3658>

gitlab-ci: add python3-requests to the test-vk container

After 90a39af5f65 ("ci: Drop the git dependency in tracie"), we have
this error in the radv-polaris10-traces job:

"
...

+ /builds/tanty/mesa/artifacts/tracie/tests/test.sh
tracie_succeeds_if_all_images_match: Fail
Traceback (most recent call last):
  File "/tmp/tracie.test.glY0O23HJo/tracie.py", line 6, in <module>
    import requests
ModuleNotFoundError: No module named 'requests'

...
"

v2:
  - Updated commit log to be more descriptive (Michel).

Fixes: 90a39af5f65 ("ci: Drop the git dependency in tracie")
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4237>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4237>

radv/llvm: fix subgroup shuffle for chips without bpermute

bpermute only exists on GFX8+ and only with Wave32 on GFX10. Instead
we have to use readlane with a waterfall loop to defeat the LLVM
backend.

This fixes DOOM Eternal which requires subgroup shuffle.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4284>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4284>

panfrost: Align Android makefiles with recent changes

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Roman Stratiienko <roman.stratiienko@nure.ua>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4280>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4280>

gitlab-ci: add a bunch of new fossils from the Sascha Vulkan demos

The whole fossils-db is only 448KB of data which is pretty small.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4082>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4082>

gitlab-ci: add a new stage for RADV CI

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4082>

gitlab-ci: compile fossils with more ASICs

I think we want to cover these 3 generations at the barely minimum.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4082>

gitlab-ci: compile fossils with both RADV compiler backends (LLVM/ACO)

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4082>

gallium/gallivm: Remove workaround disabling AVX code for newer CPUs

The change enables using full 256-bit AVX and AVX2 instructions
on newer platforms.

Reviewed-by: Alok Hota <alok.hota@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4225>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4225>

radv/winsys: spoof some values for num_render_backends in the null winsys

To avoid crashes when RADV_FORCE_FAMILY is set to GFX9+ because
num_render_backends is used to compute binning state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4282>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4282>

radv/winsys: fix wrong PCI ID for Vega10 in the null winsys

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4282>

glsl: Restore the IsES flag on the shader when reading from cache.

I found that when trying to MESA_SHADER_CAPTURE_PATH a trace, I was
getting "GLSL >= 3.00" for the ES shaders I was trying to capture.
Keeping this metadata in the cached shader program lets us capture
correctly.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4219>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4219>

gallivm: add support for rgtc/latc fetches.

Annoyingly heaven uses rgtc2 snorm but this at least avoids
the function call overheads to the util fetch functions.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3924>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3924>

gallivm/s3tc: split out dxt5 alpha code

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3924>

intel: Add TGL PCI ID

Ref: Bspec 44455
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel: Update TGL PCI strings

Ref: Bspec 44455
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

pan/bi: Pack csel4 opcodes

These are pretty straightforward but there's a lot of details to keep
straight. In the IR, we keep a general logical comparator and types
separately; in the hardware, the type gets fused with a (much more)
limited number of comparators. So there's a fair bit of code here to
account for these differences, fusing in the type information, and
changing up argument order as necessary to make it actually correct.
Anything to save a bit!

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>

pan/bi: Default csel to "!= 0" mode

This way we always have regular csel conditions instead of a weird
.always special case for 3-src CSEL mode.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>

pan/bi: Use bi_lookup_immediate when packing

This gets us part of the way there to packing lo/hi separately. A little
more work is needed to do this "properly", but hey.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>

pan/bi: Respect shift when printing immediates

We allow packing multiple immediates in, but we were missing this in the
print.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>

pan/bi: Implement csel fusing

When generating csel instructions, we can peak to see what condition is
being used. If we're using a "nice" condition, we can fuse it in with
the csel itself, ideally letting the condition itself be DCE'd away.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>

pan/bi: Add `soft` NIR->BIR condition translation

We would like to use this routine opportunistically when fusing
conditions into csels and branches, so let's add a mode where we don't
abort.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>

pan/bi: Remove hacks for 1-bit booleans in IR

Now that we lower them away, a bunch of special cases disappear.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>

pan/bi: Lower bool to ints

Currently we lower to int32, but once mediump lands we'll be ready for
that too.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>

pan/bi: Pack LD_ATTR

Also requires the usual R61/62 games.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>

pan/bi: Pack st_vary

This should let varying writes go through finally.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>

pan/bi: Add store_channels property

It can't be inferred from the usual writemask since stores don't write
to a register destination.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>

pan/bi: Generalize data register setting

So we can use it for stores too.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>

pan/bi: Flesh out st_vary IR

We need to make the semantics of BI_VECTOR a bit more precise -
vectorize only the first argument, not all of them. This is enough for
current and future users, as far as I know.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>

pan/bi: Pack ld_var_addr

Choo choo.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>

pan/bi: Pack ld_ubo ops

Routes some infrastructure to do so at least slightly generically but
we'll see.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>

pan/bi: Add bi_load32_components helper

Pattern seems to crop up a lot.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>

pan/bi: Include UBO index for sysval reads

Trivially zero.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>

pan/bi: Index out constants in instructions

We rewrite BIR_INDEX_CONSTANT (and _ZERO) to preassigned constant ports
when assign uniform_const for the bundle. There are a lot of issues
raised here, unfortunately, and the implementation here is woefully
incomplete with a nasty hack for loads... nevertheless, it's somewhere
to start.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>

pan/bi: Document constant related errata(?)

We're not totally sure what's up with this but Connor says if you
violate it Bad Things happen in your shader. I think this might be an
issue affecting early Bifrost (G71, ..?); when we know more we can look
into patching in a fix.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>

pan/bi: Pack a constant quadword

The piping isn't there to make use of it yet, but this stubs out
constant support at the clause level.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>

pan/bi: Add move lowering pass

We need ALU mostly scalarized, but we get vector moves created from
lower_vec_to_mov so let's scalarize that ourselves rather than bother
NIR.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>

pan/bi: Add bi_emit_before helper

For BIR lowering passes.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>

pan/bi: Implement FMA/MOV without modifiers

We split off MOV from FMOV since the canonical move on Bifrost doesn't
accept modifiers. (We can still do fmov, but with something like add-0.)
This will also make copyprop a little nicer, I think. Anyway, the
non-modifier version we can implement as-is for FMA.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>

etnaviv: nir: add compile_check_limits

To match TGSI compiler behaviour in glmark terrain scene for example.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4199>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4199>

ac: fix fast division

This stopped working with LLVM 11 and might occasionally have been broken
on older LLVM, because the metadata was set on the mul, not on the rcp.

Cc: 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4268>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4268>

turnip: Instance can be NULL resolving 'GetInstanceProcAddr' entry point

Using turnip driver without a vulkan loader is currently broken because
the entry point resolver is expecting a valid instance when resolving
'vkGetInstanceProcAddr' through vk_icdGetInstanceProcAddr().

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4257>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4257>

vbo,gallium: make glBegin/End buffer size configurable by drivers

The default is 512 KB, but radeonsi wants 4 MB.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4154>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4154>

glthread: remove the marshal_fail XML attribute

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>

glthread: ignore vertex arrays with user pointers if they're disabled

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>

glthread: track which vertex array attribs are enabled

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>

glthread: rename non_vbo helper functions

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>

glthread: handle buffer unbinding via glDeleteBuffers

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>

mesa: put gl_thread_state inside gl_context to remove pointer indirection

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>

glthread: rename marshal.h/c to glthread_marshal.h and glthread_shaderobj.c

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>

glthread: move buffer functions into glthread_bufferobj.c

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>

glthread: autogenerate prototypes for custom-marshalled functions

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>

glthread: simplify printing safe_mul in gl_marshal.py

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>

glthread: remove _mesa_post_marshal_hook, because it's not very useful

and also remove the useless forward declaration of enum marshal_dispatch_cmd_id.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>

util/sparse_array: Stash the node level in the node pointer

This reworks the data structure a bit and, in my view, simplifies it.
Instead of each node having a header which has the node level in it, we
use the bottom 6 bits of the pointer for that. This requires us to
allocate with the os_malloc/free_aligned helpers (which call into
posix_memalign on Linux) but cache-line aligning our allocations is
actually probably a good thing given that we're doing atomics on them.

The primary advantages to doing this is that it changes the number of
memory accesses per tree level from 2 to 1 when walking the tree because
we no longer have to look at node->level.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4228>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4228>

meson,ci: Disable sparse_array tests on windows

As soon as I switch to using the allocation helpers in os_memory.h,
these tests start blowing up on the Windows build in GitLab CI. As far
as I can tell, the issue is something with the combination of the debug
allocator in u_debug_memory.c and the mutex implementation in the
version of Wine running in CI. The tests don't fail on real windows nor
do they fail with newer versions of Wine.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4228>

util/sparse_array: Add a node_size_log2 temporary

We use this value several times. It's probably best to encourage the
compiler to only read it once. I have no proof that this actually makes
any performance improvement whatsoever.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4228>

util/sparse_array: Finish the sparse_array in the tests

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4228>

ci: Move db820c and db410c's gles3 tests to manual, like radv did.

This should make these tests available for clicking on the web ui in
personal branches, while hiding them from marge and the post-merge CI
pipelines. We had already disabled db410c's gles3, but it wasn't
available in the ui and you had to hack .gitalb-ci.yml. db820c is now
being disabled by default, due to instaboots mentioned in
https://gitlab.freedesktop.org/mesa/mesa/issues/2649

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4247>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4247>

tgsi/util: Change boolean for bool

I was getting errors with "boolean" when compiling. This patch changes
boolean to bool from <stdbool.h>.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Mark Menzynski <mmenzyns@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3903>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3903>

util/blob: Add overwrite function for uint8

Overwrite function for this type was missing and I needed it for my project.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Mark Menzynski <mmenzyns@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3903>

lima: add support for R and RG formats

Unfortunately these are not supported natively for sampling
so we have to lower them.

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4241>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4241>

lima: split pixel and texel format tables

This is preparation for the next commit where we may need different
swap_r_b flags for pixel and texel formats.

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4241>

zink/spirv: do not use bitwise operations on booleans

According to the SPIR-V specification, these operations require
integer-types. When bit_size is 1, we use booleans, which makes us emit
illegal code.

So let's fix the emitting to check if the first source is one bit wide.

For inot we can take a short-cut, and check the destination instead.
This doesn't work for ieq and ine, so let's not bother to do this
BINOP_LOG.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4036>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4036>

gitlab-ci: Restrict s390x/ppc64el jobs to packet runners

They are hitting timeouts on the gstreamer runners now... *sigh*

Reviewed-by: Adam Jackson <ajax@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4233>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4233>

radv/winsys: set has_syncobj_wait_for_submit in the null winsys

Needed for Vulkan 1.1+

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4249>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4249>

intel: add new TGL pci ids

Update following kernel : https://patchwork.freedesktop.org/patch/357921/

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bspec: 44455
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4248>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4248>

radv: fix optional pSizes parameter when binding streamout buffers

The Vulkan spec 1.2.135 says:

   "pSizes is an optional array of buffer sizes, specifying the maximum
   number of bytes to capture to the corresponding transform feedback
   buffer. If pSizes is NULL, or the value of the pSizes array element
   is VK_WHOLE_SIZE, then the maximum bytes captured will be the size
   of the corresponding buffer minus the buffer offset."

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2650
Fixes: b4eb029062a ("radv: implement VK_EXT_transform_feedback")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4232>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4232>

mesa/main: Fix overflow in validation of DispatchComputeGroupSizeARB

An uint64_t can store the result of multiplying two GLuint (uint32_t),
so use that property to check for overflow when calculating the total.

Change the error message so we don't need to care about the actual
total -- which means we don't need a larger than 64-bit value to hold
it.

Fixes: 45ab63c0cb2 ("mesa/main: add support for ARB_compute_variable_groups_size")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4240>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4240>

driconf: enable glthread for "From The Depths"

25% perf improvement

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4254>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4254>

winsys/radeon: change to 3-space indentation

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4192>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4192>

glthread: don't declare unmarshal functions as inline

They are never inlined.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4251>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4251>

glthread: clean up debug_print_sync code

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4251>

glthread: remove debug_print_marshal function

We don't need to print every function we execute.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4251>

glthread: don't execute any custom VAO and BindBuffer code in the Core profile

It's not needed, because user pointers can never occur there.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4251>