mesa.git
3 years agodri3: Stricter SBC wraparound handling
Michel Dänzer [Tue, 8 May 2018 09:51:09 +0000 (11:51 +0200)]
dri3: Stricter SBC wraparound handling

Prevents corrupting the upper 32 bits of draw->recv_sbc when
draw->send_sbc resets to 0 (which currently happens when the window is
unbound from a context and bound to one again), which in turn caused
loader_dri3_swap_buffers_msc to calculate target_msc with corrupted
upper 32 bits. This resulted in hangs with the Xorg modesetting driver
as of xserver 1.20 (older versions and other drivers ignored the upper
32 bits of the target MSC, which is why this wasn't noticed earlier).

Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/106351
Tested-by: Mike Lothian <mike@fireburn.co.uk>
3 years agoradv: fix computation of user sgprs for 32-bit pointers
Samuel Pitoiset [Mon, 21 May 2018 14:57:54 +0000 (16:57 +0200)]
radv: fix computation of user sgprs for 32-bit pointers

With 32-bit pointers we only need one user SGPR per desc set.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoradv: drop user_sgpr_info::sgpr_count
Samuel Pitoiset [Mon, 21 May 2018 14:57:53 +0000 (16:57 +0200)]
radv: drop user_sgpr_info::sgpr_count

It's only used inside allocate_user_sgprs().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoradv: add support for 32-bit pointers in user data SGPRs
Samuel Pitoiset [Wed, 16 May 2018 15:40:47 +0000 (17:40 +0200)]
radv: add support for 32-bit pointers in user data SGPRs

We still use 64-bit GPU pointers for all ring buffers because
llvm.amdgcn.implicit.buffer.ptr doesn't seem to support 32-bit
GPU pointers for now. This can be improved later anyways.

Vega10:
Totals from affected shaders:
SGPRS: 1008722 -> 1026710 (1.78 %)
VGPRS: 706580 -> 707136 (0.08 %)
Spilled SGPRs: 22555 -> 22209 (-1.53 %)
Spilled VGPRs: 75 -> 75 (0.00 %)
Code Size: 34819208 -> 35202140 (1.10 %) bytes
Max Waves: 175423 -> 175086 (-0.19 %)

Polaris10:
Totals from affected shaders:
SGPRS: 1029849 -> 1036517 (0.65 %)
VGPRS: 709984 -> 708872 (-0.16 %)
Spilled SGPRs: 22672 -> 22309 (-1.60 %)
Spilled VGPRs: 82 -> 66 (-19.51 %)
Scratch size: 76 -> 60 (-21.05 %) dwords per thread
Code Size: 34915336 -> 35309752 (1.13 %) bytes
Max Waves: 151221 -> 151677 (0.30 %)

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoradv: add set_loc_shader_ptr() helper
Samuel Pitoiset [Fri, 18 May 2018 08:57:02 +0000 (10:57 +0200)]
radv: add set_loc_shader_ptr() helper

This helper will hep for switching to 32-bit GPU pointers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoradv: allocate descriptor BOs in the 32-bit addr space
Samuel Pitoiset [Wed, 16 May 2018 15:32:57 +0000 (17:32 +0200)]
radv: allocate descriptor BOs in the 32-bit addr space

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoradv: allocate the upload BO in the 32-bit addr space
Samuel Pitoiset [Wed, 16 May 2018 15:32:38 +0000 (17:32 +0200)]
radv: allocate the upload BO in the 32-bit addr space

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoradv: set amdgpu-32bit-address-high-bits LLVM attribute
Samuel Pitoiset [Wed, 16 May 2018 14:02:04 +0000 (16:02 +0200)]
radv: set amdgpu-32bit-address-high-bits LLVM attribute

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoradv/winsys: allow to allocate BOs in the 32-bit addr space
Samuel Pitoiset [Wed, 16 May 2018 13:34:52 +0000 (15:34 +0200)]
radv/winsys: allow to allocate BOs in the 32-bit addr space

This introduces a new flag called RADEON_FLAG_32BIT.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoradv/winsys: request high address
Samuel Pitoiset [Fri, 18 May 2018 11:59:46 +0000 (13:59 +0200)]
radv/winsys: request high address

This is needed for 32-bit GPU pointers. Ported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoi965/glk: Add l3 banks count for 2x6 configuration
Anuj Phogat [Mon, 21 May 2018 22:21:56 +0000 (15:21 -0700)]
i965/glk: Add l3 banks count for 2x6 configuration

2x6 configuration with pci-id 0x3185 has same number of
banks (2) as 3x6 configuration (pci-id 0x3184).

Reported-by: Clayton Craft <clayton.a.craft@intel.com>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Tested-by: Clayton Craft <clayton.a.craft@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: eb23be1d97da "i965: Add and initialize l3_banks field for gen7+"
Cc: Francisco Jerez <currojerez@riseup.net>
3 years agov3d: Include v3d_drm.h path.
Vinson Lee [Thu, 17 May 2018 22:39:50 +0000 (22:39 +0000)]
v3d: Include v3d_drm.h path.

Fix build error.

  CC       v3d_blit.lo
In file included from v3d_blit.c:27:0:
v3d_context.h:39:10: fatal error: v3d_drm.h: No such file or directory
 #include "v3d_drm.h"
          ^~~~~~~~~~~

Fixes: 8a793d42f1cc ("v3d: Switch the vc5 driver to using the finalized V3D UABI.")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
3 years agoradv: fix centroid interpolation
Samuel Pitoiset [Mon, 21 May 2018 09:15:51 +0000 (11:15 +0200)]
radv: fix centroid interpolation

It's legal to set the centroid and sample interpolation modes
when MSAA disabled. So, we have to initialize the centroid
inputs because the hardware doesn't.

This fixes rendering issues with DXVK and The Witness, World of
Warcraft, Trackmania and probably more games.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106315
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102390
CC: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoradv: Cleanup unused prime blit path.
Bas Nieuwenhuizen [Sun, 20 May 2018 23:31:49 +0000 (01:31 +0200)]
radv: Cleanup unused prime blit path.

Since we have the common WSI code, we use vkCmdCopyImageToBuffer
instead.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agoradv: Fix SRGB compute copies.
Bas Nieuwenhuizen [Sun, 20 May 2018 23:26:46 +0000 (01:26 +0200)]
radv: Fix SRGB compute copies.

SRGB stores are broken. We had compensation code in the
resolve path but none in the copy path. Since we don't
want any conversion and it does not matter for DCC,
just make everything UNORM instead.

This happened to cause wrong colors for the PRIME path, as
that uses image->buffer copies which always use the compute
path.

CC: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106587
Reviewed-by: Dave Airlie <airlied@redhat.com>
3 years agoandroid: enable VK_ANDROID_native_buffer
Tapani Pälli [Wed, 16 May 2018 05:38:50 +0000 (08:38 +0300)]
android: enable VK_ANDROID_native_buffer

Patch changes entrypoints generator to not skip this extension even
though it is set as disabled in the xml. We also need compilation
flag VK_USE_PLATFORM_ANDROID_KHR to be enabled.

It looks like this extension got disabled in commit 69f447553c.

v2: just remove the whole 'supported' attrib check + remove
    vk_icd.h compilation fix (fix in VulkanHeaders instead)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agovulkan: update vk_icd.h to current upstream
Tapani Pälli [Fri, 18 May 2018 05:01:39 +0000 (08:01 +0300)]
vulkan: update vk_icd.h to current upstream

Import from commit eb0c1fd on branch 'master'
of https://github.com/KhronosGroup/Vulkan-Headers.git.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agovirgl: set texture buffer offset alignment to disable ARB_texture_buffer_range.
Dave Airlie [Fri, 18 May 2018 00:44:27 +0000 (10:44 +1000)]
virgl: set texture buffer offset alignment to disable ARB_texture_buffer_range.

The host side hasn't got support for this feature yet, so don't enable it
unless we get the caps from the host.

This makes the texture buffer range piglit tests skip now.

Fixes: fe0647df5a7 (virgl: add offset alignment values to to v2 caps struct)
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
3 years agomesa: stop hiding query parameters from OpenGL compat
Timothy Arceri [Fri, 18 May 2018 02:36:05 +0000 (12:36 +1000)]
mesa: stop hiding query parameters from OpenGL compat

Just let the extension detection do its job as we will be adding
compat profile support in future, also we want these to work
with compat profile version overrides.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agoradv: fix VK_EXT_descriptor_indexing
Christoph Haag [Sun, 20 May 2018 11:21:13 +0000 (13:21 +0200)]
radv: fix VK_EXT_descriptor_indexing

GetPhysicalDeviceProperties2KHR() was crashing because features was null

Fixes: 0e10790558b "radv: Enable VK_EXT_descriptor_indexing."
CC: 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoac/surface: Only align linear power of two fmt textures.
Bas Nieuwenhuizen [Fri, 18 May 2018 23:03:57 +0000 (01:03 +0200)]
ac/surface: Only align linear power of two fmt textures.

We're not sharing 32_32_32 formats between different GPUs, so we
do not have to align for vega on pre-vega cards.

Fixes: e361970ed73 "radv: Add support for IMG_DATA_FORMAT_32_32_32."
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agoamd/addrlib: Use defines in autotools build.
Bas Nieuwenhuizen [Mon, 14 May 2018 15:38:36 +0000 (17:38 +0200)]
amd/addrlib: Use defines in autotools build.

Otherwise stuff like NDEBUG would not be passed through.

CC: <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106479
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agor600/compute: Mark several functions as static
Aaron Watry [Sat, 26 Aug 2017 19:21:23 +0000 (14:21 -0500)]
r600/compute: Mark several functions as static

They're not used anywhere else, so keep them private

Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Jan Vesely <jan.vesely@rutgers.edu>
3 years agor600/compute: Remove unused compute_memory_pool functions
Aaron Watry [Sat, 26 Aug 2017 19:15:17 +0000 (14:15 -0500)]
r600/compute: Remove unused compute_memory_pool functions

Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Jan Vesely <jan.vesely@rutgers.edu>
3 years agodraw: get rid of special logic to not emit null tris
Roland Scheidegger [Thu, 17 May 2018 01:45:02 +0000 (03:45 +0200)]
draw: get rid of special logic to not emit null tris

I've confirmed after 77554d220d6d74b4d913dc37ea3a874e9dc550e4 we no
longer need this to pass some tests from another api (as we no longer
generate the bogus extra null tris in the first place).

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
3 years agodocs: Add sha sums for release
Dylan Baker [Fri, 18 May 2018 23:35:59 +0000 (16:35 -0700)]
docs: Add sha sums for release

3 years agodocs: Add release notes for 18.1.0
Dylan Baker [Fri, 18 May 2018 18:29:45 +0000 (11:29 -0700)]
docs: Add release notes for 18.1.0

3 years agonir: Implement optional b2f->iand lowering
Alyssa Rosenzweig [Wed, 2 May 2018 02:04:55 +0000 (02:04 +0000)]
nir: Implement optional b2f->iand lowering

This pass is required by the Midgard compiler; our instruction set uses
NIR-style booleans (~0 for true) but lacks a dedicated b2f instruction.
Normally, this lowering pass would be implemented in a backend-specific
algebraic pass, but this conflicts with the existing iand->b2f pass in
nir_opt_algebraic.py, hanging the compiler. This patch thus makes the
existing pass optional (default on -- all other backends should remain
unaffected), adding an optional pass for lowering the opposite
direction.

v2: Defer lowering until late algebraic optimisations to allow
optimising the b2f instruction itself.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
3 years agotravis: Adapt to radeonsi dropping support for LLVM 4
Jan Vesely [Fri, 18 May 2018 01:32:56 +0000 (21:32 -0400)]
travis: Adapt to radeonsi dropping support for LLVM 4

meson Vulkan, Clover, and autotools Vulkan need to be switched to llvm 5

Fixes: f9eb1ef870eba9fdacf9a8cbd815ec3bff81db05
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agoradeonsi: skip ES output stores for undefined output components
Marek Olšák [Thu, 17 May 2018 03:47:15 +0000 (23:47 -0400)]
radeonsi: skip ES output stores for undefined output components

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
3 years agoi965: isl: Move the MCS gen7+ assertion into ISL
Nanley Chery [Wed, 16 May 2018 18:11:04 +0000 (11:11 -0700)]
i965: isl: Move the MCS gen7+ assertion into ISL

This is useful for every user of ISL. Drop the comment along the way to
match similar functions in ISL.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
3 years agoi965/miptree: Remove format assertion in alloc_aux
Nanley Chery [Wed, 16 May 2018 18:03:24 +0000 (11:03 -0700)]
i965/miptree: Remove format assertion in alloc_aux

intel_miptree_supports_{ccs,mcs,hiz} ensures the format is valid for the
color or depth miptree before the miptree is assigned an aux_usage.
alloc_aux switches on the aux_usage so don't assert that the format is
valid.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
3 years agoi965/miptree: Simplify the switch in supports_ccs
Nanley Chery [Wed, 16 May 2018 18:07:41 +0000 (11:07 -0700)]
i965/miptree: Simplify the switch in supports_ccs

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
3 years agoi965: Make get_ccs_surf succeed in alloc_aux
Nanley Chery [Wed, 16 May 2018 17:10:35 +0000 (10:10 -0700)]
i965: Make get_ccs_surf succeed in alloc_aux

Synchronize the requirements listed in isl_surf_get_ccs_surf with
intel_miptree_supports_ccs by importing a restriction from ISL. Some
implications:
* We successfully create every aux_surf in alloc_aux
* We only return false from alloc_aux if we run out of memory

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
3 years agollvmpipe: fix check for a no-op shader
Brian Paul [Fri, 18 May 2018 01:57:21 +0000 (19:57 -0600)]
llvmpipe: fix check for a no-op shader

The tgsi_info.num_tokens fix broke llvmpipe's detection of no-op shaders.
Fix the code to check for num_instructions <= 1 instead.

Fixes: 8fde9429c36b75 ("tgsi: fix incorrect tgsi_shader_info::num_tokens
computation")
Tested-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
3 years agoradv: pass radv_nir_compiler_options directly to create_llvm_function()
Samuel Pitoiset [Fri, 18 May 2018 08:43:06 +0000 (10:43 +0200)]
radv: pass radv_nir_compiler_options directly to create_llvm_function()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
3 years agost/mesa: only define GLSL 1.4 for compat if driver supports it
Christian Gmeiner [Wed, 16 May 2018 14:02:54 +0000 (16:02 +0200)]
st/mesa: only define GLSL 1.4 for compat if driver supports it

Currently GLSL 1.4 is defined for all gallium drivers even only
GLSL 1.2 is supported as seen on etnaviv.

v1 -> v2:
 - use _min(..) as suggested by Lucas Stach and Michel Dänzer

Fixes: 4560aad780b ("mesa: add GLSLVersionCompat constant")
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
3 years agovbo: remove MaxVertexAttribStride assert check.
Dave Airlie [Tue, 15 May 2018 05:44:04 +0000 (15:44 +1000)]
vbo: remove MaxVertexAttribStride assert check.

Some drivers (virgl) don't support GL4.4 or GLES3.1 yet,
so never fill in this const.

Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Signed-off-by: Dave Airlie <airlied@redhat.com>
3 years agomesa: drop GL_EXT_polygon_offset support
Timothy Arceri [Fri, 11 May 2018 05:33:22 +0000 (15:33 +1000)]
mesa: drop GL_EXT_polygon_offset support

glPolygonOffset() has been part of the GL standard since 1.1. Also
niether AMD or Nvidia support this in their binary drivers.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61761

3 years agotgsi: fix incorrect tgsi_shader_info::num_tokens computation
Brian Paul [Thu, 17 May 2018 19:38:05 +0000 (13:38 -0600)]
tgsi: fix incorrect tgsi_shader_info::num_tokens computation

We were incrementing num_tokens in each loop iteration while parsing
the shader.  But each call to tgsi_parse_token() can consume more than
one token (and often does).  Instead, just call the tgsi_num_tokens()
function.

Luckily, this issue doesn't seem to effect any current users of this
field (llvmpipe just checks for <= 1, for example).

Reviewed-by: Neha Bhende<bhenden@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
3 years agoradv: add radv_emit_shader_pointer() helper
Samuel Pitoiset [Thu, 17 May 2018 12:08:43 +0000 (14:08 +0200)]
radv: add radv_emit_shader_pointer() helper

For future work (support for 32-bit GPU pointers).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoradv: add some helpers for cleaning up radv_get_preamble_cs()
Samuel Pitoiset [Thu, 17 May 2018 08:11:44 +0000 (10:11 +0200)]
radv: add some helpers for cleaning up radv_get_preamble_cs()

Because this function looks a bit ugly to me.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoamd: remove support for LLVM 4.0
Marek Olšák [Thu, 17 May 2018 02:23:41 +0000 (22:23 -0400)]
amd: remove support for LLVM 4.0

It doesn't support GFX9.

Acked-by: Dave Airlie <airlied@redhat.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
3 years agodocs: update calendar, add news and link release notes to 18.0.4
Juan A. Suarez Romero [Thu, 17 May 2018 18:45:26 +0000 (18:45 +0000)]
docs: update calendar, add news and link release notes to 18.0.4

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
3 years agodocs: add sha256 checksums for 18.0.4
Juan A. Suarez Romero [Thu, 17 May 2018 18:40:11 +0000 (18:40 +0000)]
docs: add sha256 checksums for 18.0.4

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit 69ef6e4a75255e60a4c4a2419d03c9352b9eb8f2)

3 years agodocs: add release notes for 18.0.4
Juan A. Suarez Romero [Thu, 17 May 2018 18:14:17 +0000 (18:14 +0000)]
docs: add release notes for 18.0.4

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit 3b49ab6219790c341ffb78a6eeaaa8b1a4b29bcc)

3 years agomesa: The glArrayElement api is independent of the current program.
Mathias Fröhlich [Sun, 13 May 2018 07:18:57 +0000 (09:18 +0200)]
mesa: The glArrayElement api is independent of the current program.

All the shader program dependent handling is done on the level
of the gl_Context::Array._DrawVAO/_DrawVAOEnabledAttribs.
So, skip array element invalidation on _NEW_PROGRAM.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
3 years agomesa: Flag _NEW_ARRAY only if we are changing ctx->Array.VAO.
Mathias Fröhlich [Sun, 13 May 2018 07:18:57 +0000 (09:18 +0200)]
mesa: Flag _NEW_ARRAY only if we are changing ctx->Array.VAO.

For the VAO internal helper functions that may be called
with a non current VAO, flag the _NEW_ARRAY state only
if it is the current ctx->Array.VAO.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
3 years agomesa: Remove flush_vertices argument from VAO methods.
Mathias Fröhlich [Sun, 13 May 2018 07:18:57 +0000 (09:18 +0200)]
mesa: Remove flush_vertices argument from VAO methods.

The flush_vertices argument is now unused, remove it.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
3 years agomesa: Remove FLUSH_VERTICES from VAO state changes.
Mathias Fröhlich [Sun, 13 May 2018 07:18:57 +0000 (09:18 +0200)]
mesa: Remove FLUSH_VERTICES from VAO state changes.

Pending draw calls on immediate mode or display list calls do
not depend on changes of the VAO state. So, remove calls to
FLUSH_VERTICES and flag _NEW_ARRAY as appropriate.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
3 years agodocs: add 18.0.5 in the release calendar
Juan A. Suarez Romero [Mon, 14 May 2018 14:17:38 +0000 (16:17 +0200)]
docs: add 18.0.5 in the release calendar

Mesa 18.1 series has not been released yet, so let's extend 18.0 lifetime.

v2: Add missing closing TR tags (Eric Engestrom)

CC: Andres Gomez <agomez@igalia.com>
CC: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
3 years agoswr/rast: Added FEClipRectangles event
Alok Hota [Wed, 16 May 2018 16:14:21 +0000 (11:14 -0500)]
swr/rast: Added FEClipRectangles event

and also added some comments

Reviewed-By: George Kyriazis <george.kyriazis@intel.com>
3 years agoswr/rast: Whitespace and tab-to-spaces changes
Alok Hota [Wed, 16 May 2018 16:14:20 +0000 (11:14 -0500)]
swr/rast: Whitespace and tab-to-spaces changes

Reviewed-By: George Kyriazis <george.kyriazis@intel.com>
3 years agoswr/rast: fix VCVTPD2PS generation for AVX512
Alok Hota [Wed, 16 May 2018 16:14:19 +0000 (11:14 -0500)]
swr/rast: fix VCVTPD2PS generation for AVX512

Reviewed-By: George Kyriazis <george.kyriazis@intel.com>
3 years agoswr/rast: Rectlist support for GS
Alok Hota [Wed, 16 May 2018 16:14:18 +0000 (11:14 -0500)]
swr/rast: Rectlist support for GS

Add rectlist as an option for GS.  Needed to support some driver
optimizations.

Reviewed-By: George Kyriazis <george.kyriazis@intel.com>
3 years agoswr/rast: Remove unneeded virtual from methods
Alok Hota [Wed, 16 May 2018 16:14:17 +0000 (11:14 -0500)]
swr/rast: Remove unneeded virtual from methods

Reviewed-By: George Kyriazis <george.kyriazis@intel.com>
3 years agobroadcom/vc4: Native fence fd support
Stefan Schake [Tue, 24 Apr 2018 22:01:00 +0000 (00:01 +0200)]
broadcom/vc4: Native fence fd support

With the syncobj support in place, lets use it to implement the
EGL_ANDROID_native_fence_sync extension. This mostly follows previous
implementations in freedreno and etnaviv.

v2: Drop the flags (Eric)
    Handle in_fence_fd already in job_submit (Eric)
    Drop extra vc4_fence_context_init (Eric)
    Dup fds with CLOEXEC (Eric)
    Mention exact extension name (Eric)

Signed-off-by: Stefan Schake <stschake@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
3 years agobroadcom/vc4: Store job fence in syncobj
Stefan Schake [Tue, 24 Apr 2018 22:00:59 +0000 (00:00 +0200)]
broadcom/vc4: Store job fence in syncobj

This gives us access to the fence created for the render job.

v2: Drop flag (Eric)

Signed-off-by: Stefan Schake <stschake@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
3 years agobroadcom/vc4: Detect syncobj support
Stefan Schake [Tue, 24 Apr 2018 22:00:58 +0000 (00:00 +0200)]
broadcom/vc4: Detect syncobj support

We need to know if the kernel supports syncobj submission since otherwise
all the DRM syncobj calls fail.

v2: Use drmGetCap to detect syncobj support (Eric)

Signed-off-by: Stefan Schake <stschake@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
3 years agobroadcom/vc4: Bump libdrm requirement
Stefan Schake [Tue, 24 Apr 2018 22:00:57 +0000 (00:00 +0200)]
broadcom/vc4: Bump libdrm requirement

Require a version of libdrm with syncobj support.

v2: Don't require a libdrm_vc4, just bump core libdrm if vc4 enabled (by
    anholt)

Signed-off-by: Stefan Schake <stschake@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
3 years agodrm-uapi: Update vc4 header with syncobj submit support
Stefan Schake [Tue, 24 Apr 2018 22:00:56 +0000 (00:00 +0200)]
drm-uapi: Update vc4 header with syncobj submit support

v2: Synchronized with kernel v2
v3: Update for the finalized kernel ABI (pad2 field)

Signed-off-by: Stefan Schake <stschake@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
3 years agobroadcom/vc4: Drop libdrm_vc4 requirement
Stefan Schake [Tue, 24 Apr 2018 22:00:55 +0000 (00:00 +0200)]
broadcom/vc4: Drop libdrm_vc4 requirement

This was missed in the move back to the local uapi copy.
libdrm_vc4 only seems to consist of headers that also exist in the
Mesa tree.

Signed-off-by: Stefan Schake <stschake@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
3 years agov3d: Add support for glSampleMask / glSampleCoverage.
Eric Anholt [Tue, 8 May 2018 21:28:33 +0000 (14:28 -0700)]
v3d: Add support for glSampleMask / glSampleCoverage.

3 years agov3d: Enable NaN propagation in the VS and CS as well.
Eric Anholt [Tue, 8 May 2018 20:22:57 +0000 (13:22 -0700)]
v3d: Enable NaN propagation in the VS and CS as well.

Fixes piglit vs-isnan-*.shader_test at the expense of gl-1.0-spot-light.

3 years agoi965/blorp: Disable BLORP clear color updates
Nanley Chery [Fri, 27 Apr 2018 00:13:36 +0000 (17:13 -0700)]
i965/blorp: Disable BLORP clear color updates

With the previous patches, we now update the indirect clear color buffer
every time the clear color changes. Avoid redundant updates.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agointel/blorp: Add a NO_UPDATE_CLEAR_COLOR batch flag
Nanley Chery [Fri, 27 Apr 2018 00:09:29 +0000 (17:09 -0700)]
intel/blorp: Add a NO_UPDATE_CLEAR_COLOR batch flag

Allow callers to handle updating the indirect clear color buffer
themselves. This can reduce the number of clear color updates in the
case where a caller performs multiple fast clears with the same clear
color.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agoi965/blorp: Also skip the fast clear if the clear color differs
Nanley Chery [Tue, 27 Mar 2018 22:08:53 +0000 (15:08 -0700)]
i965/blorp: Also skip the fast clear if the clear color differs

If the aux state is CLEAR and clear color value has changed, only the
surface state must be updated. The bit-pattern in the aux buffer is
exactly the same.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agoi965/clear: Drop a stale comment in fast_clear_depth
Nanley Chery [Sun, 8 Apr 2018 21:00:30 +0000 (14:00 -0700)]
i965/clear: Drop a stale comment in fast_clear_depth

This comment made more sense when it was above the calls to
intel_miptree_slice_set_needs_depth_resolve(). We stopped using these
functions at commit 554f7d6d02931ea45653c8872565d21c1678a6da
("i965: Move depth to the new resolve functions").

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agoi965: Update the indirect buffer in set_clear_color
Nanley Chery [Sun, 8 Apr 2018 21:00:30 +0000 (14:00 -0700)]
i965: Update the indirect buffer in set_clear_color

For depth buffers, we avoid fast-clearing if the aux_state is already
CLEAR. We do the same for color buffers only if the clear color
doesn't change. We require that the clear colors match because, in
that case, we don't update the indirect clear color outside of BLORP.

Update the indirect clear color for color buffers as well. We'll
enable the same depth buffer optimization for color buffers in a
later patch.

Note that we're now actually updating the indirect clear color twice
in the case where we use BLORP to perform the fast-clear. This is
only temporary. In later patches, we'll prevent BLORP from performing
the update.

v2: Add more context to the commit message (Topi).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
3 years agoi965/clear: Remove an early return in fast_clear_depth
Nanley Chery [Wed, 25 Apr 2018 00:16:50 +0000 (17:16 -0700)]
i965/clear: Remove an early return in fast_clear_depth

Reduce complexity and allow the next patch to delete some code. With
this change, clear operations will still be skipped and setting the
aux_state will cause no side-effects.

Remove the associated comment which implies an early return.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agoi965: Use set_clear_color for depth miptrees
Nanley Chery [Fri, 27 Apr 2018 01:49:19 +0000 (18:49 -0700)]
i965: Use set_clear_color for depth miptrees

Reduce code duplication now and prevent it in the following commits.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agoRevert "i965: Make the miptree clear color setter take a gl_color_union"
Nanley Chery [Fri, 27 Apr 2018 19:27:07 +0000 (12:27 -0700)]
Revert "i965: Make the miptree clear color setter take a gl_color_union"

This reverts commit 1d94aa19877fb702ffacacde28ad7253cce72c97.

The next patch will make depth miptrees use the clear color setter that
was originally being used for color miptrees. Go back to using the
isl_color_value parameter because it's the same type as the
fast_clear_color field used by color and depth miptrees.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agoi965/miptree: Unify aux buffer allocation
Nanley Chery [Tue, 1 May 2018 00:00:32 +0000 (17:00 -0700)]
i965/miptree: Unify aux buffer allocation

There isn't much that changes between the aux allocation functions.
Remove the duplicated code.

v2: Inline the switch statement (Jason).

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agoi965: Prepare to delete intel_miptree_alloc_ccs()
Nanley Chery [Thu, 3 May 2018 03:05:08 +0000 (20:05 -0700)]
i965: Prepare to delete intel_miptree_alloc_ccs()

We're going to delete intel_miptree_alloc_ccs() in the next commit. With
that in mind, replace the use of this function in
do_single_blorp_clear() with intel_miptree_alloc_aux() and move the
delayed allocation logic to it's callers.

v2: Duplicate the delayed allocation comment (Topi Pohjolainen).

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agoi965/miptree: Drop the mt param from alloc_aux_buffer
Nanley Chery [Wed, 2 May 2018 21:30:17 +0000 (14:30 -0700)]
i965/miptree: Drop the mt param from alloc_aux_buffer

Drop an unused parameter.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agoi965/miptree: Drop the alloc_flags param from alloc_aux_buffer
Nanley Chery [Wed, 2 May 2018 19:46:54 +0000 (12:46 -0700)]
i965/miptree: Drop the alloc_flags param from alloc_aux_buffer

We have enough information to determine the optimal flags internally.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agoi965/miptree: Drop the name param from alloc_aux_buffer
Nanley Chery [Tue, 1 May 2018 21:35:35 +0000 (14:35 -0700)]
i965/miptree: Drop the name param from alloc_aux_buffer

A name of "aux-miptree" should be sufficient.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agoi965/miptree: Initialize the indirect clear color to zero
Nanley Chery [Mon, 30 Apr 2018 18:30:32 +0000 (11:30 -0700)]
i965/miptree: Initialize the indirect clear color to zero

The indirect clear color isn't correctly tracked in
intel_miptree::fast_clear_color. The initial value of ::fast_clear_color
is zero, while that of the indirect clear color is undefined.

Topi Pohjolainen discovered this issue with MCS buffers. This issue is
apparent when fast-clearing an MCS buffer for the first time with
glClearColor = {0.0,}. Although the indirect clear color is undefined,
the initial aux state of the MCS is CLEAR and the tracked clear color is
zero, so we avoid updating the indirect clear color with {0.0,}.

Make the indirect clear color match the initial value of
::fast_clear_color.

Note: although we only have to drop HiZ's BO_ALLOC_BUSY flag for gen10+,
we also drop it pre-gen10 to keep things simple. We add this flag back
for pre-gen10 in a later patch.

v2: Add a note about dropping HiZ's BO_ALLOC_BUSY flag (Topi).

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agoi965/miptree: Add and use a memset option in alloc_aux_buffer
Nanley Chery [Mon, 30 Apr 2018 17:44:01 +0000 (10:44 -0700)]
i965/miptree: Add and use a memset option in alloc_aux_buffer

Add infrastructure for initializing the clear color BO.
intel_miptree_init_mcs is no longer needed with change.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agoi965/miptree: Zero-initialize CCS_D buffers
Nanley Chery [Wed, 2 May 2018 16:38:47 +0000 (09:38 -0700)]
i965/miptree: Zero-initialize CCS_D buffers

Before this patch, the aux_state was actually AUX_INVALID because the BO
was never defined. This was fine on single slice miptrees because we
would fast-clear the resource right after creation. For multi-slice
miptrees on SKL+ however, this results in undefined behavior when
accessing a non-base slice. Here's a specific example:

1) Fast clear level 0
   * Undefined CCS_D buffer allocated in "PASS_THROUGH" state.
   * Level 0 transitions to the CLEAR state.
2) Render to level 1
   * Level 1 may have a 2-bit pattern of 2's.
   * Rendering with a 2 in the CCS is undefined.

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agoi965/miptree: Fix handling of uninitialized MCS buffers
Nanley Chery [Mon, 30 Apr 2018 17:40:18 +0000 (10:40 -0700)]
i965/miptree: Fix handling of uninitialized MCS buffers

Before this patch, if we failed to initialize an MCS buffer, we'd
end up in a state in which the miptree thinks it has an MCS buffer,
but doesn't. We also leaked the clear_color_bo if it existed.

With this patch, we now free the miptree aux buffer resources and let
intel_miptree_alloc_mcs() know that the MCS buffer no longer exists.

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
3 years agoradv: only declare the ESGS rings for pre GFX9 chips
Samuel Pitoiset [Tue, 15 May 2018 20:27:28 +0000 (22:27 +0200)]
radv: only declare the ESGS rings for pre GFX9 chips

GFX9 uses LDS instead.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoradv: allow to print GPU info with RADV_DEBUG=info
Samuel Pitoiset [Wed, 16 May 2018 13:52:37 +0000 (15:52 +0200)]
radv: allow to print GPU info with RADV_DEBUG=info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoradv: do not emit unnecessary ES output stores
Samuel Pitoiset [Wed, 16 May 2018 15:43:23 +0000 (17:43 +0200)]
radv: do not emit unnecessary ES output stores

GFX9:
Totals from affected shaders:
SGPRS: 472 -> 464 (-1.69 %)
VGPRS: 576 -> 584 (1.39 %)
Code Size: 45432 -> 44324 (-2.44 %) bytes
Max Waves: 40 -> 40 (0.00 %)

VI:
SGPRS: 720 -> 720 (0.00 %)
VGPRS: 728 -> 728 (0.00 %)
Code Size: 45348 -> 43992 (-2.99 %) bytes
Max Waves: 120 -> 120 (0.00 %)

This affects Rise of Tomb Raider and the three Vulkan demos
that use a geometry shader (geometryshader, deferredshadows
and viewportarray).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoradv: do not emit unnecessary GS output stores
Samuel Pitoiset [Wed, 16 May 2018 15:43:22 +0000 (17:43 +0200)]
radv: do not emit unnecessary GS output stores

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoradv: only pass the global BO list at submit time if enabled
Samuel Pitoiset [Thu, 17 May 2018 09:36:09 +0000 (11:36 +0200)]
radv: only pass the global BO list at submit time if enabled

That way the winsys might use a faster path when the global
BO list is NULL.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoradv: remove the radv_finishme() when compiling shaders
Samuel Pitoiset [Thu, 17 May 2018 07:56:48 +0000 (09:56 +0200)]
radv: remove the radv_finishme() when compiling shaders

Having an entrypoint different than "main" doesn't mean we
have multiple shaders per module.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agoradv: remove radv_device::llvm_supports_spill
Samuel Pitoiset [Thu, 17 May 2018 07:56:47 +0000 (09:56 +0200)]
radv: remove radv_device::llvm_supports_spill

It's always true.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
3 years agomesa: add glUniform*ui{v} support to display lists
Timothy Arceri [Thu, 10 May 2018 03:42:16 +0000 (13:42 +1000)]
mesa: add glUniform*ui{v} support to display lists

Fixes: a017c7ecb7ae "mesa: display list support for uint uniforms"
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78097

3 years agoradeonsi: create .gitignore
Dieter Nützel [Sun, 13 May 2018 20:51:14 +0000 (22:51 +0200)]
radeonsi: create .gitignore

Signed-off-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
3 years agoac/llvm: use amdgcn.tbuffer.store instead of SI.tbuffer.store intrinsic
Dave Airlie [Tue, 15 May 2018 23:36:22 +0000 (09:36 +1000)]
ac/llvm: use amdgcn.tbuffer.store instead of SI.tbuffer.store intrinsic

Drop the use of the old intrinsic.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
3 years agov3d: Fix wiring filters to NEAREST for 32-bit texture returns.
Eric Anholt [Wed, 2 May 2018 00:22:09 +0000 (17:22 -0700)]
v3d: Fix wiring filters to NEAREST for 32-bit texture returns.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104626

3 years agov3d: Enable the driver by default.
Eric Anholt [Tue, 1 May 2018 19:20:11 +0000 (12:20 -0700)]
v3d: Enable the driver by default.

Now that we have a stabilized ABI and a fairly conformant driver, turn it
on.

3 years agov3d: Rename driver functions from vc5 to v3d.
Eric Anholt [Tue, 1 May 2018 19:39:31 +0000 (12:39 -0700)]
v3d: Rename driver functions from vc5 to v3d.

This is the final step of the driver rename.

3 years agov3d: Rename the driver files from "vc5" to "v3d".
Eric Anholt [Tue, 1 May 2018 19:24:48 +0000 (12:24 -0700)]
v3d: Rename the driver files from "vc5" to "v3d".

3 years agov3d: Rename the vc5_dri.so driver to v3d_dri.so.
Eric Anholt [Fri, 25 Aug 2017 22:34:22 +0000 (15:34 -0700)]
v3d: Rename the vc5_dri.so driver to v3d_dri.so.

This allows the driver to load against the merged kernel DRM driver.  In
the process, rename most of the build system variables and gallium
plumbing functions.

3 years agov3d: Switch the vc5 driver to using the finalized V3D UABI.
Eric Anholt [Tue, 1 May 2018 19:00:56 +0000 (12:00 -0700)]
v3d: Switch the vc5 driver to using the finalized V3D UABI.

In the process of merging to the kernel, I renamed the driver to the
general product line's name (since we have both vc5 and vc6 supported
already).  Since the ABI is finalized, move the header to include/drm-uapi.

3 years agosvga: fix incompatible bind flags at buffer validation time
Charmaine Lee [Fri, 11 May 2018 18:21:52 +0000 (11:21 -0700)]
svga: fix incompatible bind flags at buffer validation time

At buffer resource validation time, if the resource handle is not yet
created and if the initial buffer bind flags and the tobind flags are
incompatible, just use the tobind flags to create the resource handle.
On the other hand, if the bind flags are compatible, we can combine
the bind flags for the resource handle creation.

Fixes piglit gl-3.1-buffer-bindings crash.

Reviewed-by: Brian Paul <brianp@vmware.com>
3 years agomesa: cast the GLenum16 to GLint to avoid compile warning on android
jenny.q.cao [Wed, 16 May 2018 07:02:00 +0000 (01:02 -0600)]
mesa: cast the GLenum16 to GLint to avoid compile warning on android

Cast the enum to GLint to avoid the compile warning:
/src/mesa/main/get.c:3005:19:
warning: comparison of constant -32768 with expression of type
'GLenum16' (aka 'unsigned short') is always false
-Wtautologicalia-constant-out-of-range-compare

Tests: compilation without this warning
Signed-off-by: jenny.q.cao <jenny.q.cao@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
3 years agoetnaviv: Fix missing rnndb file in tarballs
Stuart Young [Wed, 16 May 2018 17:01:43 +0000 (03:01 +1000)]
etnaviv: Fix missing rnndb file in tarballs

Seems that when the rnndb files for etniviv were updated/included back
in Nov 2017, hw/texdesc_3d.xml.h was missed from Makefile.sources and
meson.build. This was all during the conversion to meson, so it apears
to have slipped through the cracks. As such, this file has been missing
from the official tarballs since inclusion in Mesa, so the git trees
and tarballs differ.

Found due to lintian errors in the Debian packages.

Fixes: f1e1c60ff6 ("etnaviv: Update from rnndb")
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>