From 04ea4f1ce474e7fceb24cbebab01d51d7e8c1e61 Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Mon, 20 Jul 2020 19:21:20 +0100 Subject: [PATCH] aco: implement b2i8/b2i16 MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Fixes lots of tests under dEQP-VK.spirv_assembly.type.* Signed-off-by: Rhys Perry Reviewed-by: Daniel Schürmann Part-of: --- src/amd/compiler/aco_instruction_selection.cpp | 17 ++++++++++++----- .../aco_instruction_selection_setup.cpp | 3 +++ 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index c94a1b00e5e..e8fd15c293a 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -2693,18 +2693,25 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr) break; } case nir_op_b2b32: - case nir_op_b2i32: { + case nir_op_b2i8: + case nir_op_b2i16: + case nir_op_b2i32: + case nir_op_b2i64: { Temp src = get_alu_src(ctx, instr->src[0]); assert(src.regClass() == bld.lm); - if (dst.regClass() == s1) { + Temp tmp = dst.bytes() == 8 ? bld.tmp(RegClass::get(dst.type(), 4)) : dst; + if (tmp.regClass() == s1) { // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ - bool_to_scalar_condition(ctx, src, dst); - } else if (dst.regClass() == v1) { - bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), src); + bool_to_scalar_condition(ctx, src, tmp); + } else if (tmp.type() == RegType::vgpr) { + bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(tmp), Operand(0u), Operand(1u), src); } else { unreachable("Invalid register class for b2i32"); } + + if (tmp != dst) + bld.pseudo(aco_opcode::p_create_vector, Definition(dst), tmp, Operand(0u)); break; } case nir_op_b2b1: diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp index aab5cc3488e..72b4f38b826 100644 --- a/src/amd/compiler/aco_instruction_selection_setup.cpp +++ b/src/amd/compiler/aco_instruction_selection_setup.cpp @@ -532,7 +532,10 @@ void init_context(isel_context *ctx, nir_shader *shader) case nir_op_f2u32: case nir_op_f2i64: case nir_op_f2u64: + case nir_op_b2i8: + case nir_op_b2i16: case nir_op_b2i32: + case nir_op_b2i64: case nir_op_b2b32: case nir_op_b2f16: case nir_op_b2f32: -- 2.30.2