From 3b9fbcb3b6caee65f15dd2876d8dabc590eb0d70 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Nicolai=20H=C3=A4hnle?= Date: Wed, 12 Apr 2017 10:16:07 +0200 Subject: [PATCH 1/1] radeonsi: change the bit-packing of LS out/TCS in data MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Avoid conflicts when merging various VS state bits. Reviewed-by: Marek Olšák --- src/gallium/drivers/radeonsi/si_shader.c | 10 +++++----- src/gallium/drivers/radeonsi/si_shader.h | 9 +++++++-- src/gallium/drivers/radeonsi/si_state_draw.c | 4 ++-- 3 files changed, 14 insertions(+), 9 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index a1dc4b34702..5c17c640a3c 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -227,9 +227,9 @@ static LLVMValueRef get_tcs_in_patch_stride(struct si_shader_context *ctx) { if (ctx->type == PIPE_SHADER_VERTEX) - return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13); + return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 8, 13); else if (ctx->type == PIPE_SHADER_TESS_CTRL) - return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13); + return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 8, 13); else { assert(0); return NULL; @@ -923,7 +923,7 @@ static LLVMValueRef fetch_input_tcs( struct si_shader_context *ctx = si_shader_context(bld_base); LLVMValueRef dw_addr, stride; - stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8); + stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 24, 8); dw_addr = get_tcs_in_current_patch_offset(ctx); dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr); @@ -2408,7 +2408,7 @@ static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base) buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds); - lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8); + lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 24, 8); lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id, lds_vertex_stride, ""); lds_base = get_tcs_in_current_patch_offset(ctx); @@ -2663,7 +2663,7 @@ static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base) LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn, ctx->param_rel_auto_id); LLVMValueRef vertex_dw_stride = - unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8); + unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 24, 8); LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id, vertex_dw_stride, ""); diff --git a/src/gallium/drivers/radeonsi/si_shader.h b/src/gallium/drivers/radeonsi/si_shader.h index 4a0f2704564..6ce2b26c974 100644 --- a/src/gallium/drivers/radeonsi/si_shader.h +++ b/src/gallium/drivers/radeonsi/si_shader.h @@ -175,8 +175,9 @@ enum { SI_PARAM_TCS_OUT_LAYOUT, /* Layout of LS outputs / TCS inputs - * [0:12] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4 - * [13:20] = stride between vertices in dwords = num_inputs * 4, max = 32*4 + * [8:20] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4 + * [24:31] = stride between vertices in dwords = num_inputs * 4, max = 32*4 + * (same layout as SI_PARAM_VS_STATE_BITS) */ SI_PARAM_TCS_IN_LAYOUT, @@ -230,6 +231,10 @@ enum { /* Clamp vertex color output (only used in VS as VS). */ #define S_VS_STATE_CLAMP_VERTEX_COLOR(x) (((unsigned)(x) & 0x1) << 0) #define C_VS_STATE_CLAMP_VERTEX_COLOR 0xFFFFFFFE +#define S_VS_STATE_LS_OUT_PATCH_SIZE(x) (((unsigned)(x) & 0x1FFF) << 8) +#define C_VS_STATE_LS_OUT_PATCH_SIZE 0xFFE000FF +#define S_VS_STATE_LS_OUT_VERTEX_SIZE(x) (((unsigned)(x) & 0xFF) << 24) +#define C_VS_STATE_LS_OUT_VERTEX_SIZE 0x00FFFFFF /* SI-specific system values. */ enum { diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 54e02d217a9..7bf4f4ddb87 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -212,8 +212,8 @@ static void si_emit_derived_tess_state(struct si_context *sctx, assert(num_tcs_input_cp <= 32); assert(num_tcs_output_cp <= 32); - tcs_in_layout = (input_patch_size / 4) | - ((input_vertex_size / 4) << 13); + tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) | + S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4); tcs_out_layout = (output_patch_size / 4) | ((output_vertex_size / 4) << 13); tcs_out_offsets = (output_patch0_offset / 16) | -- 2.30.2