From 9c21002f6ed0621fbd68f413eceb58a89ace7275 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Wed, 20 Jun 2018 18:15:36 -0500 Subject: [PATCH] radeonsi: handle non-clearable DCC buffers as MSAA resolve dst This is reproducible on Stoney, but other chips may be affected too. Cc 18.1 Reviewed-by: Bas Nieuwenhuizen --- src/gallium/drivers/radeonsi/si_blit.c | 5 +++++ src/gallium/drivers/radeonsi/si_clear.c | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c index 194e181adfc..9024717791c 100644 --- a/src/gallium/drivers/radeonsi/si_blit.c +++ b/src/gallium/drivers/radeonsi/si_blit.c @@ -1161,6 +1161,11 @@ static bool do_hardware_msaa_resolve(struct pipe_context *ctx, info->dst.resource->last_level != 0) goto resolve_to_temp; + /* This can happen with mipmapping. */ + if (sctx->chip_class == VI && + !dst->surface.u.legacy.level[info->dst.level].dcc_fast_clear_size) + goto resolve_to_temp; + vi_dcc_clear_level(sctx, dst, info->dst.level, 0xFFFFFFFF); dst->dirty_level_mask &= ~(1 << info->dst.level); diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c index 72319b3eca2..53c255c5808 100644 --- a/src/gallium/drivers/radeonsi/si_clear.c +++ b/src/gallium/drivers/radeonsi/si_clear.c @@ -479,7 +479,7 @@ static void si_do_fast_color_clear(struct si_context *sctx, if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR)) continue; - /* This can only occur with MSAA. */ + /* This can happen with mipmapping or MSAA. */ if (sctx->chip_class == VI && !tex->surface.u.legacy.level[level].dcc_fast_clear_size) continue; -- 2.30.2