From b4de9e035ac0afe64ebfd58cd0eb04c1a671afce Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Fri, 31 Jul 2020 10:31:50 -0400 Subject: [PATCH] pan/mdg: Mask spills from texture write This prevents RA failures the results of reading multiple textures that require less than 4 channels, as seen in a number of GL 3 WebRender shaders. Closes: #3342 Signed-off-by: Alyssa Rosenzweig Reported-by: Icecream95 Tested-by: Icecream95 Cc: mesa-stable Part-of: --- src/panfrost/midgard/midgard_ra.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/panfrost/midgard/midgard_ra.c b/src/panfrost/midgard/midgard_ra.c index 1b8c8c3d2de..b06eb97ab8e 100644 --- a/src/panfrost/midgard/midgard_ra.c +++ b/src/panfrost/midgard/midgard_ra.c @@ -855,9 +855,17 @@ mir_spill_register( midgard_instruction st; + /* Note: it's important to match the mask of the spill + * with the mask of the instruction whose destination + * we're spilling, or otherwise we'll read invalid + * components and can fail RA in a subsequent iteration + */ + if (is_special_w) { st = v_mov(spill_node, spill_slot); st.no_spill |= (1 << spill_class); + st.mask = ins->mask; + st.dest_type = st.src_types[0] = ins->dest_type; } else { ins->dest = spill_index++; ins->no_spill |= (1 << spill_class); -- 2.30.2