From c84e2784eb205c7cf9c74b9dbcd5a1b657f93aa4 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Thu, 20 Aug 2020 23:59:54 -0500 Subject: [PATCH] intel/nir: Allow splitting a single load into up to 32 loads Reviewed-by: Kenneth Graunke Part-of: --- src/intel/compiler/brw_nir_lower_mem_access_bit_sizes.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_nir_lower_mem_access_bit_sizes.c b/src/intel/compiler/brw_nir_lower_mem_access_bit_sizes.c index f67a414e873..c26ea0bb778 100644 --- a/src/intel/compiler/brw_nir_lower_mem_access_bit_sizes.c +++ b/src/intel/compiler/brw_nir_lower_mem_access_bit_sizes.c @@ -109,8 +109,10 @@ lower_mem_load_bit_size(nir_builder *b, nir_intrinsic_instr *intrin, result = nir_extract_bits(b, &load, 1, load_offset * 8, num_components, bit_size); } else { - /* Otherwise, we have to break it into smaller loads */ - nir_ssa_def *loads[8]; + /* Otherwise, we have to break it into smaller loads. We could end up + * with as many as 32 loads if we're loading a u64vec16 from scratch. + */ + nir_ssa_def *loads[32]; unsigned num_loads = 0; int load_offset = 0; while (load_offset < bytes_read) { -- 2.30.2