From cdb21dfffa1300b1032619bc44da99c970fd3f56 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sun, 8 Oct 2017 18:20:38 +0200 Subject: [PATCH] radeonsi: handle 64-bit loads earlier in fetch_constant MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_shader.c | 26 +++++++++--------------- 1 file changed, 10 insertions(+), 16 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 62a056dce43..ff372ae0531 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -1977,7 +1977,6 @@ static LLVMValueRef fetch_constant( unsigned buf, idx; LLVMValueRef addr, bufp; - LLVMValueRef result; if (swizzle == LP_CHAN_ALL) { unsigned chan; @@ -1988,6 +1987,15 @@ static LLVMValueRef fetch_constant( return lp_build_gather_values(&ctx->gallivm, values, 4); } + /* Split 64-bit loads. */ + if (tgsi_type_is_64bit(type)) { + LLVMValueRef lo, hi; + + lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle); + hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle + 1); + return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi); + } + assert(reg->Register.Dimension); buf = reg->Dimension.Index; idx = reg->Register.Index * 4 + swizzle; @@ -2010,21 +2018,7 @@ static LLVMValueRef fetch_constant( addr = LLVMConstInt(ctx->i32, idx * 4, 0); } - result = buffer_load_const(ctx, bufp, addr); - - if (!tgsi_type_is_64bit(type)) - result = bitcast(bld_base, type, result); - else { - LLVMValueRef addr2, result2; - - addr2 = lp_build_add(&bld_base->uint_bld, addr, - LLVMConstInt(ctx->i32, 4, 0)); - result2 = buffer_load_const(ctx, bufp, addr2); - - result = si_llvm_emit_fetch_64bit(bld_base, type, - result, result2); - } - return result; + return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr)); } /* Upper 16 bits must be zero. */ -- 2.30.2