From d7b65cf7d3d51124be590a1b66fb89f94f723fe3 Mon Sep 17 00:00:00 2001 From: Karol Herbst Date: Sat, 7 Mar 2020 16:55:19 +0100 Subject: [PATCH] nv50/ir: fix cas lowering for 64 bit Signed-off-by: Karol Herbst Part-of: --- .../drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp index 52106cb931f..0e69f25ca28 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp @@ -1734,9 +1734,10 @@ NVC0LoweringPass::handleCasExch(Instruction *cas, bool needCctl) // happen elsewhere in the universe. // Also, it sometimes returns the new value instead of the old one // under mysterious circumstances. - Value *dreg = bld.getSSA(8); + DataType ty = typeOfSize(typeSizeof(cas->dType) * 2); + Value *dreg = bld.getSSA(typeSizeof(ty)); bld.setPosition(cas, false); - bld.mkOp2(OP_MERGE, TYPE_U64, dreg, cas->getSrc(1), cas->getSrc(2)); + bld.mkOp2(OP_MERGE, ty, dreg, cas->getSrc(1), cas->getSrc(2)); cas->setSrc(1, dreg); cas->setSrc(2, dreg); } -- 2.30.2