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2010-08-20	Zhenyu Wang	i965: Set the destination horiz stride even for da16...	commit \| commitdiff \| tree
2010-08-20	Zhenyu Wang	i965: Set the maximum number of threads on Sandybridge.	commit \| commitdiff \| tree
2010-08-20	Zhenyu Wang	i965: Add AccWrCtl support on Sandybridge.	commit \| commitdiff \| tree
2010-08-20	Zhenyu Wang	i965: Mention the mlen and rlen for URB reads.	commit \| commitdiff \| tree
2010-08-20	Zhenyu Wang	i965: Sandybridge doesn't have Compr4 mode, since it...	commit \| commitdiff \| tree
2010-08-20	Zhenyu Wang	i965: Adjust disasm of subreg numbers to be in units...	commit \| commitdiff \| tree
2010-07-08	Zhenyu Wang	i965: Add 'wait' instruction support Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>	commit \| commitdiff \| tree
2010-07-08	Zhenyu Wang	i965: Add decode for Sandybridge DP write messages.	commit \| commitdiff \| tree
2010-07-08	Zhenyu Wang	i965: Add definitions for Sandybridge DP write/read...	commit \| commitdiff \| tree
2010-06-14	Zhenyu Wang	i965: correct the gen6 line stipple enable define.	commit \| commitdiff \| tree
2010-06-13	Zhenyu Wang	i965: Use the new message header format for FF_SYNC...	commit \| commitdiff \| tree
2010-06-13	Zhenyu Wang	i965: Add support for math instructions in the gen6 WM.	commit \| commitdiff \| tree
2010-06-13	Zhenyu Wang	i965: Set the correct WM GRF start reg on gen6.	commit \| commitdiff \| tree
2010-04-21	Zhenyu Wang	intel: Add Sandybridge mobile chipset id Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>	commit \| commitdiff \| tree
2010-04-21	Zhenyu Wang	intel: Clean up chipset name and gen num for Ironlake Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>	commit \| commitdiff \| tree
2009-09-10	Zhenyu Wang	intel: add B43 chipset support Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>	commit \| commitdiff \| tree
2009-09-09	Zhenyu Wang	intel: add B43 chipset support Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>	commit \| commitdiff \| tree

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