2 GHDLFLAGS
=--std
=08 -frelaxed
8 NEXTPNR ?
= nextpnr-ecp5
12 # We need a version of GHDL built with either the LLVM or gcc backend.
13 # Fedora provides this, but other distros may not. Another option is to use
28 ifeq ($(USE_DOCKER
), 1)
30 DOCKERARGS
= run
--rm -v
$(PWD
):/src
:z
-w
/src
31 GHDL
= $(DOCKERBIN
) $(DOCKERARGS
) ghdl
/ghdl
:buster-llvm-7 ghdl
32 CC
= $(DOCKERBIN
) $(DOCKERARGS
) ghdl
/ghdl
:buster-llvm-7 gcc
34 YOSYS
= $(DOCKERBIN
) $(DOCKERARGS
) hdlc
/ghdl
:yosys yosys
35 NEXTPNR
= $(DOCKERBIN
) $(DOCKERARGS
) hdlc
/nextpnr
:ecp5 nextpnr-ecp5
36 ECPPACK
= $(DOCKERBIN
) $(DOCKERARGS
) hdlc
/prjtrellis ecppack
37 OPENOCD
= $(DOCKERBIN
) $(DOCKERARGS
) --device
/dev
/bus
/usb hdlc
/prog openocd
40 all = core_tb icache_tb dcache_tb multiply_tb dmi_dtm_tb divider_tb \
41 rotator_tb countzero_tb wishbone_bram_tb soc_reset_tb
45 core_files
= decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl \
46 utils.vhdl plru.vhdl cache_ram.vhdl icache.vhdl \
47 decode1.vhdl helpers.vhdl insn_helpers.vhdl \
48 control.vhdl decode2.vhdl register_file.vhdl \
49 cr_file.vhdl crhelpers.vhdl ppc_fx_insns.vhdl rotator.vhdl \
50 logical.vhdl countzero.vhdl multiply.vhdl divider.vhdl execute1.vhdl \
51 loadstore1.vhdl mmu.vhdl dcache.vhdl writeback.vhdl core_debug.vhdl \
54 _soc_files
= wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \
55 wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl \
56 spi_rxtx.vhdl spi_flash_ctrl.vhdl
58 soc_files
= $(core_files
) $(_soc_files
)
60 uart_files
= $(wildcard uart16550
/*.v
)
62 soc_sim_files
= $(soc_files
) sim_console.vhdl sim_pp_uart.vhdl sim_bram_helpers.vhdl \
63 sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl dmi_dtm_xilinx.vhdl \
65 random.vhdl glibc_random.vhdl glibc_random_helpers.vhdl
67 soc_sim_c_files
= sim_vhpi_c.c sim_bram_helpers_c.c sim_console_c.c \
70 soc_sim_obj_files
=$(soc_sim_c_files
:.c
=.o
)
72 soc_sim_link
=$(patsubst %,-Wl
$(comma
)%,$(soc_sim_obj_files
))
74 unisim_dir
= sim-unisim
75 unisim_lib
= $(unisim_dir
)/unisim-obj08.cf
76 unisim_lib_files
= $(unisim_dir
)/BSCANE2.vhdl
$(unisim_dir
)/BUFG.vhdl \
77 $(unisim_dir
)/unisim_vcomponents.vhdl
78 $(unisim_lib
): $(unisim_lib_files
)
79 $(GHDL
) -i
--std
=08 --work
=unisim
--workdir
=$(unisim_dir
) $^
80 GHDLFLAGS
+= -P
$(unisim_dir
)
82 core_tbs
= multiply_tb divider_tb rotator_tb countzero_tb
83 soc_tbs
= core_tb icache_tb dcache_tb dmi_dtm_tb wishbone_bram_tb
84 soc_flash_tbs
= core_flash_tb
85 soc_dram_tbs
= dram_tb core_dram_tb
87 ifneq ($(FLASH_MODEL_PATH
),)
88 fmf_dir
= $(FLASH_MODEL_PATH
)/fmf
89 fmf_lib
= $(fmf_dir
)/fmf-obj08.cf
90 fmf_lib_files
= $(wildcard $(fmf_dir
)/*.vhd
)
91 GHDLFLAGS
+= -P
$(fmf_dir
)
92 $(fmf_lib
): $(fmf_lib_files
)
93 $(GHDL
) -i
--std
=08 --work
=fmf
--workdir
=$(fmf_dir
) $^
95 flash_model_files
=$(FLASH_MODEL_PATH
)/s25fl128s.vhd
96 flash_model_files
: $(fmf_lib
)
98 flash_model_files
=sim_no_flash.vhdl
102 $(soc_flash_tbs
): %: $(soc_sim_files
) $(soc_sim_obj_files
) $(unisim_lib
) $(fmf_lib
) $(flash_model_files
) %.vhdl
103 $(GHDL
) -c
$(GHDLFLAGS
) $(soc_sim_link
) $(soc_sim_files
) $(flash_model_files
) $@.vhdl
$(unisim_files
) -e
$@
105 $(soc_tbs
): %: $(soc_sim_files
) $(soc_sim_obj_files
) $(unisim_lib
) %.vhdl
106 $(GHDL
) -c
$(GHDLFLAGS
) $(soc_sim_link
) $(soc_sim_files
) $@.vhdl
-e
$@
108 $(core_tbs
): %: $(core_files
) glibc_random.vhdl glibc_random_helpers.vhdl
%.vhdl
109 $(GHDL
) -c
$(GHDLFLAGS
) $(core_files
) glibc_random.vhdl glibc_random_helpers.vhdl
$@.vhdl
-e
$@
111 soc_reset_tb
: fpga
/soc_reset_tb.vhdl fpga
/soc_reset.vhdl
112 $(GHDL
) -c
$(GHDLFLAGS
) fpga
/soc_reset_tb.vhdl fpga
/soc_reset.vhdl
-e
$@
115 VERILATOR_ROOT
=$(shell verilator
-getenv VERILATOR_ROOT
2>/dev
/null
)
116 ifeq (, $(VERILATOR_ROOT
))
118 $(error
"Verilator is required to make this target !")
123 verilated_dram
: litedram
/generated
/sim
/litedram_core.v
124 verilator
$(VERILATOR_FLAGS
) -CFLAGS
$(VERILATOR_CFLAGS
) -Wno-fatal
--cc $< --trace
125 make
-C obj_dir
-f ..
/litedram
/extras
/sim_dram_verilate.mk VERILATOR_ROOT
=$(VERILATOR_ROOT
)
127 SIM_DRAM_CFLAGS
= -I.
-Iobj_dir
-Ilitedram
/generated
/sim
-I
$(VERILATOR_ROOT
)/include -I
$(VERILATOR_ROOT
)/include/vltstd
128 SIM_DRAM_CFLAGS
+= -DVM_COVERAGE
=0 -DVM_SC
=0 -DVM_TRACE
=1 -DVL_PRINTF
=printf
-faligned-new
129 sim_litedram_c.o
: litedram
/extras
/sim_litedram_c.
cpp verilated_dram
130 $(CC
) $(CPPFLAGS
) $(SIM_DRAM_CFLAGS
) $(CFLAGS
) -c
$< -o
$@
132 soc_dram_files
= $(soc_files
) litedram
/extras
/litedram-wrapper-l2.vhdl litedram
/generated
/sim
/litedram-initmem.vhdl
133 soc_dram_sim_files
= $(soc_sim_files
) litedram
/extras
/sim_litedram.vhdl
134 soc_dram_sim_obj_files
= $(soc_sim_obj_files
) sim_litedram_c.o
135 dram_link_files
=-Wl
,obj_dir
/Vlitedram_core__ALL.a
-Wl
,obj_dir
/verilated.o
-Wl
,obj_dir
/verilated_vcd_c.o
-Wl
,-lstdc
++
136 soc_dram_sim_link
=$(patsubst %,-Wl
$(comma
)%,$(soc_dram_sim_obj_files
)) $(dram_link_files
)
138 $(soc_dram_tbs
): %: $(soc_dram_files
) $(soc_dram_sim_files
) $(soc_dram_sim_obj_files
) $(flash_model_files
) $(unisim_lib
) $(fmf_lib
) %.vhdl
139 $(GHDL
) -c
$(GHDLFLAGS
) $(soc_dram_sim_link
) $(soc_dram_files
) $(soc_dram_sim_files
) $(flash_model_files
) $@.vhdl
-e
$@
144 RAM_INIT_FILE
=hello_world
/hello_world.hex
149 #RAM_INIT_FILE=micropython/firmware.hex
152 #MEMORY_SIZE=536870912
153 #RAM_INIT_FILE=dtbImage.microwatt.hex
155 SIM_BRAM_CHAINBOOT
=6291456 # 0x600000
157 FPGA_TARGET ?
= ORANGE-CRAB
159 clkgen
=fpga
/clk_gen_ecp5.vhd
160 toplevel
=fpga
/top-generic.vhdl
161 dmi_dtm
=dmi_dtm_dummy.vhdl
164 ifeq ($(FPGA_TARGET
), ULX3S
)
167 CLK_FREQUENCY
=12500000
168 LPF
=constraints
/ulx3s.lpf
170 NEXTPNR_FLAGS
=--85k
--freq
25
171 OPENOCD_JTAG_CONFIG
=openocd
/ulx3s.cfg
172 OPENOCD_DEVICE_CONFIG
=openocd
/LFE5U-85F.cfg
173 toplevel
=fpga
/top-ulx3s.vhdl
176 # OrangeCrab with ECP85
177 ifeq ($(FPGA_TARGET
), ORANGE-CRAB
)
180 CLK_FREQUENCY
=40000000
181 LPF
=constraints
/orange-crab.lpf
183 NEXTPNR_FLAGS
=--um5g-85k
--freq
40
184 OPENOCD_JTAG_CONFIG
=openocd
/olimex-arm-usb-tiny-h.cfg
185 OPENOCD_DEVICE_CONFIG
=openocd
/LFE5UM5G-85F.cfg
189 ifeq ($(FPGA_TARGET
), ECP5-EVN
)
192 CLK_FREQUENCY
=40000000
193 LPF
=constraints
/ecp5-evn.lpf
195 NEXTPNR_FLAGS
=--um5g-85k
--freq
40
196 OPENOCD_JTAG_CONFIG
=openocd
/ecp5-evn.cfg
197 OPENOCD_DEVICE_CONFIG
=openocd
/LFE5UM5G-85F.cfg
202 ifeq ($(FPGA_TARGET
), verilator
)
205 CLK_FREQUENCY
=50000000
206 clkgen
=fpga
/clk_gen_bypass.vhd
209 FPGA_MAIN_BRAM
=fpga
/main_bram.vhdl
212 _fpga_files
= fpga
/soc_reset.vhdl \
213 fpga
/pp_fifo.vhd fpga
/pp_soc_uart.vhd
$(FPGA_MAIN_BRAM
) \
216 # use an alternative core (in verilog)
218 # VHDL does not allow integers greater than 2^32, so shift down
219 # by 16 bits and add 16 bits zeros back on in soc-generic.vhdl
220 RESET_ADDRESS
=65280 # 0xff00_0000>>16
221 ifeq ($(EXTERNAL_CORE
),false
)
222 fpga_files
= $(_fpga_files
) $(_soc_files
) $(core_files
)
223 synth_files
= $(core_files
) $(soc_files
) $(fpga_files
) $(clkgen
) $(toplevel
) $(dmi_dtm
)
225 util_files
= decode_types.vhdl common.vhdl wishbone_types.vhdl utils.vhdl \
227 fpga_files
= $(_fpga_files
) $(_soc_files
)
228 synth_files
= $(util_files
) $(fpga_files
) $(clkgen
) $(toplevel
) $(dmi_dtm
)
229 soc_extra_v
= external_core_top.v
232 GHDL_IMAGE_GENERICS
=-gMEMORY_SIZE
=$(MEMORY_SIZE
) \
233 -gRAM_INIT_FILE
=$(RAM_INIT_FILE
) \
234 -gRESET_LOW
=$(RESET_LOW
) \
235 -gRESET_ADDRESS
=$(RESET_ADDRESS
) \
236 -gCLK_INPUT
=$(CLK_INPUT
) \
237 -gCLK_FREQUENCY
=$(CLK_FREQUENCY
) \
238 -gSIM_MAIN_BRAM
=$(SIM_MAIN_BRAM
) \
239 -gSIM_BRAM_CHAINBOOT
=$(SIM_BRAM_CHAINBOOT
) \
240 -gEXTERNAL_CORE
=$(EXTERNAL_CORE
)
242 microwatt.json
: $(synth_files
) $(RAM_INIT_FILE
)
243 $(YOSYS
) -m
$(GHDLSYNTH
) -p \
244 "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) \
245 $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; \
246 read_verilog $(uart_files) $(soc_extra_v); \
247 synth_ecp5 -top toplevel -nowidelut -json $@ $(SYNTH_ECP5_FLAGS)"
249 microwatt.v
: $(synth_files
) $(RAM_INIT_FILE
)
250 $(YOSYS
) -m
$(GHDLSYNTH
) -p
"ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
252 # Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall
253 # --top-module toplevel
254 microwatt-verilator
: microwatt.v verilator
/microwatt-verilator.
cpp verilator
/uart-verilator.c
255 verilator
-O3
-CFLAGS
"-DCLK_FREQUENCY=$(CLK_FREQUENCY) -I../verilator" \
258 --exe verilator
/microwatt-verilator.
cpp verilator
/uart-verilator.c \
260 -Wno-fatal
-Wno-CASEOVERLAP
-Wno-UNOPTFLAT \
263 -Wno-CASEINCOMPLETE \
267 # --unroll-count 256 \
268 # --output-split 5000 \
269 # --output-split-cfuncs 500 \
270 # --output-split-ctrace 500 \
271 make
-C obj_dir
-f Vmicrowatt.mk
272 @cp
-f obj_dir
/microwatt-verilator microwatt-verilator
274 microwatt_out.config
: microwatt.json
$(LPF
)
275 $(NEXTPNR
) --json
$< --lpf
$(LPF
) --lpf-allow-unconstrained \
276 --textcfg
$@.tmp
$(NEXTPNR_FLAGS
) --package
$(PACKAGE
)
279 microwatt.bit
: microwatt_out.config
280 $(ECPPACK
) --svf microwatt.svf
$< $@
282 microwatt.svf
: microwatt.bit
285 $(OPENOCD
) -f
$(OPENOCD_JTAG_CONFIG
) -f
$(OPENOCD_DEVICE_CONFIG
) -c
"transport select jtag; init; svf $<; exit"
287 tests
= $(sort $(patsubst tests
/%.out
,%,$(wildcard tests
/*.out
)))
288 tests_console
= $(sort $(patsubst tests
/%.console_out
,%,$(wildcard tests
/*.console_out
)))
290 tests_console
: $(tests_console
)
292 check: $(tests
) tests_console test_micropython test_micropython_long tests_unit
294 check_light
: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 test_micropython test_micropython_long tests_console tests_unit
297 @.
/scripts
/run_test.sh
$@
299 $(tests_console
): core_tb
300 @.
/scripts
/run_test_console.sh
$@
302 test_micropython
: core_tb
303 @.
/scripts
/test_micropython.py
305 test_micropython_long
: core_tb
306 @.
/scripts
/test_micropython_long.py
308 tests_core_tb
= $(patsubst %_tb
,%_tb_test
,$(core_tbs
))
309 tests_soc_tb
= $(patsubst %_tb
,%_tb_test
,$(soc_tbs
))
312 .
/$< --assert-level
=error
> /dev
/null
314 tests_core
: $(tests_core_tb
)
316 tests_soc
: $(tests_soc_tb
)
318 # FIXME SOC tests have bit rotted, so disable for now
319 #tests_unit: tests_core tests_soc
320 tests_unit
: tests_core
323 find .
-name
'*.vhdl' | xargs .
/scripts
/vhdltags
328 rm -f
*.o
*.cf
$(all)
329 rm -f fpga
/*.o fpga
/*.cf
330 rm -f sim-unisim
/*.o sim-unisim
/*.cf
331 rm -f litedram
/extras
/*.o
333 rm -f scripts
/mw_debug
/*.o
334 rm -f scripts
/mw_debug
/mw_debug
335 rm -f microwatt.bin microwatt.json microwatt.svf microwatt_out.config
336 rm -f microwatt.v microwatt-verilator
340 make
-f scripts
/mw_debug
/Makefile
clean
341 make
-f hello_world
/Makefile
clean
344 rm -f
*~ fpga
/*~ lib
/*~ console
/*~
include/*~
345 rm -rf litedram
/build
346 rm -f litedram
/extras
/*~
347 rm -f litedram
/gen-src
/*~
348 rm -f litedram
/gen-src
/sdram_init
/*~
349 make
-f scripts
/mw_debug
/Makefile
distclean
350 make
-f hello_world
/Makefile
distclean
352 .PHONY
: all prog
check check_light
clean distclean
353 .PRECIOUS
: microwatt.json microwatt_out.config microwatt.bit