Forgot to remove dissasembly file.
[microwatt.git] / fpga / top-generic.vhdl
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4
5 library work;
6 use work.wishbone_types.all;
7 use work.utils.all;
8
9 entity toplevel is
10 generic (
11 MEMORY_SIZE : positive := (384*1024);
12 RAM_INIT_FILE : string := "firmware.hex";
13 RESET_LOW : boolean := true;
14 PLL_RESET_BITS : positive := 18;
15 EXTERNAL_CORE : boolean := false;
16 SIM_MAIN_BRAM : boolean := false;
17 SIM_BRAM_CHAINBOOT : positive := 0;
18 RESET_ADDRESS : integer := 0;
19 CLK_INPUT : positive := 100000000;
20 CLK_FREQUENCY : positive := 100000000;
21 HAS_FPU : boolean := true;
22 HAS_BTC : boolean := false;
23 LOG_LENGTH : natural := 512;
24 DISABLE_FLATTEN_CORE : boolean := false;
25 UART_IS_16550 : boolean := true;
26 HAS_UART1 : boolean := false
27 );
28 port(
29 ext_clk : in std_ulogic;
30 ext_rst : in std_ulogic;
31
32 -- UART0 signals:
33 uart0_txd : out std_ulogic;
34 uart0_rxd : in std_ulogic;
35
36 -- BRAM verilator access
37 bram_we : out std_ulogic;
38 bram_re : out std_ulogic;
39 bram_addr : out std_logic_vector(log2ceil(MEMORY_SIZE) - 3- 1 downto 0);
40 bram_di : out std_logic_vector(63 downto 0);
41 bram_do : in std_logic_vector(63 downto 0);
42 bram_sel : out std_logic_vector(7 downto 0);
43
44 -- for verilator debugging
45 nia_req: out std_ulogic;
46 nia: out std_ulogic_vector(63 downto 0);
47 msr_o: out std_ulogic_vector(63 downto 0);
48 insn: out std_ulogic_vector(31 downto 0);
49 ldst_req: out std_ulogic;
50 ldst_addr: out std_ulogic_vector(63 downto 0)
51 );
52 end entity toplevel;
53
54 architecture behaviour of toplevel is
55
56 -- Reset signals:
57 signal soc_rst : std_ulogic;
58 signal pll_rst : std_ulogic;
59
60 -- Internal clock signals:
61 signal system_clk : std_ulogic;
62 signal system_clk_locked : std_ulogic;
63
64 begin
65
66 reset_controller: entity work.soc_reset
67 generic map(
68 RESET_LOW => RESET_LOW,
69 PLL_RESET_BITS => PLL_RESET_BITS
70 )
71 port map(
72 ext_clk => ext_clk,
73 pll_clk => system_clk,
74 pll_locked_in => system_clk_locked,
75 ext_rst_in => ext_rst,
76 pll_rst_out => pll_rst,
77 rst_out => soc_rst
78 );
79
80 clkgen: entity work.clock_generator
81 generic map(
82 CLK_INPUT_HZ => CLK_INPUT,
83 CLK_OUTPUT_HZ => CLK_FREQUENCY
84 )
85 port map(
86 ext_clk => ext_clk,
87 pll_rst_in => pll_rst,
88 pll_clk_out => system_clk,
89 pll_locked_out => system_clk_locked
90 );
91
92 -- Main SoC
93 soc0: entity work.soc
94 generic map(
95 MEMORY_SIZE => MEMORY_SIZE,
96 SIM_BRAM_CHAINBOOT => SIM_BRAM_CHAINBOOT,
97 SIM_MAIN_BRAM => SIM_MAIN_BRAM,
98 EXTERNAL_CORE => EXTERNAL_CORE,
99 RAM_INIT_FILE => RAM_INIT_FILE,
100 SIM => false,
101 CLK_FREQ => CLK_FREQUENCY,
102 HAS_FPU => HAS_FPU,
103 HAS_BTC => HAS_BTC,
104 LOG_LENGTH => LOG_LENGTH,
105 DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,
106 UART0_IS_16550 => UART_IS_16550,
107 HAS_UART1 => HAS_UART1,
108 RESET_ADDRESS => (std_ulogic_vector(to_unsigned(RESET_ADDRESS, 48)
109 & x"0000"))
110 )
111 port map (
112 system_clk => system_clk,
113 rst => soc_rst,
114 uart0_txd => uart0_txd,
115 uart0_rxd => uart0_rxd,
116 bram_we => bram_we,
117 bram_re => bram_re,
118 bram_addr => bram_addr,
119 bram_di => bram_di,
120 bram_do => bram_do,
121 bram_sel => bram_sel,
122 nia_req => nia_req,
123 nia => nia,
124 msr_o => msr_o,
125 insn => insn,
126 ldst_req => ldst_req,
127 ldst_addr => ldst_addr
128 );
129
130 end architecture behaviour;