include/microwatt_soc.h

   1 #ifndef __MICROWATT_SOC_H
   2 #define __MICROWATT_SOC_H
   3
   4 /*
   5  * Microwatt SoC memory map
   6  */
   7
   8 #define MEMORY_BASE     0x00000000  /* "Main" memory alias, either BRAM or DRAM */
   9 #define DRAM_BASE       0x40000000  /* DRAM if present */
  10 #define BRAM_BASE       0x80000000  /* Internal BRAM */
  11
  12 #define SYSCON_BASE     0xc0000000  /* System control regs */
  13 #define UART_BASE       0xc0002000  /* UART */
  14 #define XICS_ICP_BASE   0xc0004000  /* Interrupt controller */
  15 #define XICS_ICS_BASE   0xc0005000  /* Interrupt controller */
  16 #define SPI_FCTRL_BASE  0xc0006000  /* SPI flash controller registers */
  17 #define DRAM_CTRL_BASE  0xc8000000  /* LiteDRAM control registers */
  18 #define LETH_CSR_BASE   0xc8020000  /* LiteEth CSR registers */
  19 #define LETH_SRAM_BASE  0xc8030000  /* LiteEth MMIO space */
  20 #define SPI_FLASH_BASE  0xf0000000  /* SPI Flash memory map */
  21 #ifdef STANDALONE_MINI_BIOS
  22 #define DRAM_INIT_BASE  0x00000000  /* alternative, for verilator simulation */
  23 #else
  24 #define DRAM_INIT_BASE  0xff000000  /* Internal DRAM init firmware */
  25 #endif
  26
  27 /*
  28  * Interrupt numbers
  29  */
  30 #define IRQ_UART0       0
  31 #define IRQ_ETHERNET    1
  32
  33 /*
  34  * Register definitions for the syscon registers
  35  */
  36
  37 #define SYS_REG_SIGNATURE               0x00
  38 #define SYS_REG_INFO                    0x08
  39 #define   SYS_REG_INFO_HAS_UART                 (1ull << 0)
  40 #define   SYS_REG_INFO_HAS_DRAM                 (1ull << 1)
  41 #define   SYS_REG_INFO_HAS_BRAM                 (1ull << 2)
  42 #define   SYS_REG_INFO_HAS_SPI_FLASH            (1ull << 3)
  43 #define   SYS_REG_INFO_HAS_LITEETH              (1ull << 4)
  44 #define   SYS_REG_INFO_HAS_LARGE_SYSCON         (1ull << 5)
  45 #define   SYS_REG_INFO_HAS_UART1                (1ull << 6)
  46 #define   SYS_REG_INFO_HAS_ARTB                 (1ull << 7)
  47 #define SYS_REG_BRAMINFO                0x10
  48 #define   SYS_REG_BRAMINFO_SIZE_MASK            0xfffffffffffffull
  49 #define SYS_REG_DRAMINFO                0x18
  50 #define   SYS_REG_DRAMINFO_SIZE_MASK            0xfffffffffffffull
  51 #define SYS_REG_CLKINFO                 0x20
  52 #define   SYS_REG_CLKINFO_FREQ_MASK             0xffffffffffull
  53 #define SYS_REG_CTRL                    0x28
  54 #define   SYS_REG_CTRL_DRAM_AT_0                (1ull << 0)
  55 #define   SYS_REG_CTRL_CORE_RESET               (1ull << 1)
  56 #define   SYS_REG_CTRL_SOC_RESET                (1ull << 2)
  57 #define SYS_REG_DRAMINITINFO            0x30
  58 #define SYS_REG_SPI_INFO                0x38
  59 #define   SYS_REG_SPI_INFO_FLASH_OFF_MASK       0xffffffff
  60 #define SYS_REG_UART0_INFO              0x40
  61 #define SYS_REG_UART1_INFO              0x48
  62 #define   SYS_REG_UART_IS_16550                 (1ull << 32)
  63 #define SYS_REG_BRAM_BOOTADDR           0x50
  64
  65
  66 /*
  67  * Register definitions for the potato UART
  68  */
  69 #define POTATO_CONSOLE_TX               0x00
  70 #define POTATO_CONSOLE_RX               0x08
  71 #define POTATO_CONSOLE_STATUS           0x10
  72 #define   POTATO_CONSOLE_STATUS_RX_EMPTY                0x01
  73 #define   POTATO_CONSOLE_STATUS_TX_EMPTY                0x02
  74 #define   POTATO_CONSOLE_STATUS_RX_FULL                 0x04
  75 #define   POTATO_CONSOLE_STATUS_TX_FULL                 0x08
  76 #define POTATO_CONSOLE_CLOCK_DIV        0x18
  77 #define POTATO_CONSOLE_IRQ_EN           0x20
  78 #define   POTATO_CONSOLE_IRQ_RX                         0x01
  79 #define   POTATO_CONSOLE_IRQ_TX                         0x02
  80
  81 /*
  82  * Register definitionss for our standard (16550 style) UART
  83  */
  84 #define UART_REG_RX       0x00
  85 #define UART_REG_TX       0x00
  86 #define UART_REG_DLL      0x00
  87 #define UART_REG_IER      0x04
  88 #define   UART_REG_IER_RDI      0x01
  89 #define   UART_REG_IER_THRI     0x02
  90 #define   UART_REG_IER_RLSI     0x04
  91 #define   UART_REG_IER_MSI      0x08
  92 #define UART_REG_DLM      0x04
  93 #define UART_REG_IIR      0x08
  94 #define UART_REG_FCR      0x08
  95 #define   UART_REG_FCR_EN_FIFO  0x01
  96 #define   UART_REG_FCR_CLR_RCVR 0x02
  97 #define   UART_REG_FCR_CLR_XMIT 0x04
  98 #define   UART_REG_FCR_TRIG1    0x00
  99 #define   UART_REG_FCR_TRIG4    0x40
 100 #define   UART_REG_FCR_TRIG8    0x80
 101 #define   UART_REG_FCR_TRIG14   0xc0
 102 #define UART_REG_LCR      0x0c
 103 #define   UART_REG_LCR_5BIT     0x00
 104 #define   UART_REG_LCR_6BIT     0x01
 105 #define   UART_REG_LCR_7BIT     0x02
 106 #define   UART_REG_LCR_8BIT     0x03
 107 #define   UART_REG_LCR_STOP     0x04
 108 #define   UART_REG_LCR_PAR      0x08
 109 #define   UART_REG_LCR_EVEN_PAR 0x10
 110 #define   UART_REG_LCR_STIC_PAR 0x20
 111 #define   UART_REG_LCR_BREAK    0x40
 112 #define   UART_REG_LCR_DLAB     0x80
 113 #define UART_REG_MCR      0x10
 114 #define   UART_REG_MCR_DTR      0x01
 115 #define   UART_REG_MCR_RTS      0x02
 116 #define   UART_REG_MCR_OUT1     0x04
 117 #define   UART_REG_MCR_OUT2     0x08
 118 #define   UART_REG_MCR_LOOP     0x10
 119 #define UART_REG_LSR      0x14
 120 #define   UART_REG_LSR_DR       0x01
 121 #define   UART_REG_LSR_OE       0x02
 122 #define   UART_REG_LSR_PE       0x04
 123 #define   UART_REG_LSR_FE       0x08
 124 #define   UART_REG_LSR_BI       0x10
 125 #define   UART_REG_LSR_THRE     0x20
 126 #define   UART_REG_LSR_TEMT     0x40
 127 #define   UART_REG_LSR_FIFOE    0x80
 128 #define UART_REG_MSR      0x18
 129 #define UART_REG_SCR      0x1c
 130
 131
 132 /*
 133  * Register definitions for the SPI controller
 134  */
 135 #define SPI_REG_DATA                    0x00 /* Byte access: single wire transfer */
 136 #define SPI_REG_DATA_DUAL               0x01 /* Byte access: dual wire transfer */
 137 #define SPI_REG_DATA_QUAD               0x02 /* Byte access: quad wire transfer */
 138 #define SPI_REG_CTRL                    0x04 /* Reset and manual mode control */
 139 #define   SPI_REG_CTRL_RESET                    0x01  /* reset all registers */
 140 #define   SPI_REG_CTRL_MANUAL_CS                0x02  /* assert CS, enable manual mode */
 141 #define   SPI_REG_CTRL_CKDIV_SHIFT              8     /* clock div */
 142 #define   SPI_REG_CTRL_CKDIV_MASK               (0xff << SPI_REG_CTRL_CKDIV_SHIFT)
 143 #define SPI_REG_AUTO_CFG                0x08 /* Automatic map configuration */
 144 #define   SPI_REG_AUTO_CFG_CMD_SHIFT            0     /* Command to use for reads */
 145 #define   SPI_REG_AUTO_CFG_CMD_MASK             (0xff << SPI_REG_AUTO_CFG_CMD_SHIFT)
 146 #define   SPI_REG_AUTO_CFG_DUMMIES_SHIFT        8     /* # dummy cycles */
 147 #define   SPI_REG_AUTO_CFG_DUMMIES_MASK         (0x7  << SPI_REG_AUTO_CFG_DUMMIES_SHIFT)
 148 #define   SPI_REG_AUTO_CFG_MODE_SHIFT           11    /* SPI wire mode */
 149 #define   SPI_REG_AUTO_CFG_MODE_MASK            (0x3  << SPI_REG_AUTO_CFG_MODE_SHIFT)
 150 #define     SPI_REG_AUT_CFG_MODE_SINGLE         (0 << 11)
 151 #define     SPI_REG_AUT_CFG_MODE_DUAL           (2 << 11)
 152 #define     SPI_REG_AUT_CFG_MODE_QUAD           (3 << 11)
 153 #define   SPI_REG_AUTO_CFG_ADDR4                (1u << 13) /* 3 or 4 addr bytes */
 154 #define   SPI_REG_AUTO_CFG_CKDIV_SHIFT          16    /* clock div */
 155 #define   SPI_REG_AUTO_CFG_CKDIV_MASK           (0xff << SPI_REG_AUTO_CFG_CKDIV_SHIFT)
 156 #define   SPI_REG_AUTO_CFG_CSTOUT_SHIFT         24    /* CS timeout */
 157 #define   SPI_REG_AUTO_CFG_CSTOUT_MASK          (0x3f << SPI_REG_AUTO_CFG_CSTOUT_SHIFT)
 158
 159
 160 #endif /* __MICROWATT_SOC_H */