tercel/wishbone_spi_master.v

   1 // © 2017 - 2022 Raptor Engineering, LLC
   2 //
   3 // Released under the terms of the GNU LGPL v3
   4 // See the LICENSE file for full details
   5
   6 // =============================================================================================
   7 // Memory Map:
   8 // =============================================================================================
   9 // Device ID string (8 bytes)
  10 // Device version (4 bytes)
  11 // Base clock frequency (4 bytes)
  12 // PHY configuration register 1 (4 bytes): {cs_extra_idle_cycles, 2'b0, qspi_write_quad_io_en, qspi_read_quad_io_en, fast_read_mode, four_byte_address_mode, phy_io_type, dummy_cycle_count, spi_clock_divisor}
  13 // Flash configuration register 1 (4 bytes): {4BA QSPI read command, 3BA QSPI read command, 4BA SPI read command, 3BA SPI read command}
  14 // Flash configuration register 2 (4 bytes): {4BA QSPI fast read command, 3BA QSPI fast read command, 4BA SPI fast read command, 3BA SPI fast read command}
  15 // Flash configuration register 3 (4 bytes): {4BA QSPI program command, 3BA QSPI program command, 4BA SPI program command, 3BA SPI program command}
  16 // Flash configuration register 4 (4 bytes): {spi_cs_active_hold_cycles}
  17 // Flash configuration register 5 (4 bytes): {30'b0, allow_multicycle_writes, allow_multicycle_reads}
  18 // Control register 1 (4 bytes): {31'b0, user_command_mode}
  19 // Data register 1 (4 bytes): {24'b0, user_command_mode_read_during_write}
  20
  21 // Stop LiteX silently ignoring net naming / missing register errors
  22 `default_nettype none
  23
  24 module tercel_core(
  25                 // Configuration registers
  26                 input wire [31:0] sys_clk_freq,
  27
  28                 // Wishbone signals
  29                 input wire wishbone_cyc,
  30                 input wire wishbone_stb,
  31                 input wire wishbone_we,
  32                 input wire [29:0] wishbone_adr,
  33                 input wire [31:0] wishbone_dat_w,
  34                 output wire [31:0] wishbone_dat_r,
  35                 input wire [3:0] wishbone_sel,
  36                 output wire wishbone_ack,
  37                 output wire wishbone_err,
  38
  39                 // Wishbone configuration port signals
  40                 input wire cfg_wishbone_cyc,
  41                 input wire cfg_wishbone_stb,
  42                 input wire cfg_wishbone_we,
  43                 input wire [29:0] cfg_wishbone_adr,
  44                 input wire [31:0] cfg_wishbone_dat_w,
  45                 output wire [31:0] cfg_wishbone_dat_r,
  46                 input wire [3:0] cfg_wishbone_sel,
  47                 output wire cfg_wishbone_ack,
  48                 output wire cfg_wishbone_err,
  49
  50                 // SPI bus signals
  51                 output wire spi_clock,
  52                 output wire [3:0] spi_d_out,
  53                 output wire [3:0] spi_d_direction,                      // 0 == tristate (input), 1 == driven (output)
  54                 input wire [3:0] spi_d_in,
  55                 output wire spi_ss_n,
  56
  57                 output wire [7:0] debug_port,
  58
  59                 input wire peripheral_reset,
  60                 input wire peripheral_clock
  61         );
  62
  63         // Control and status registers
  64         wire [63:0] device_id;
  65         wire [31:0] device_version;
  66
  67         // PHY configuration register 1
  68         // Defaults to standard SPI mode, 3BA, non-extended read/write (qspi_[read|write]_quad_io_en = 0), cs_extra_idle_cycles = 0, dummy cycle cont = 10, clock divisor 16
  69         reg [31:0] phy_cfg1 = 32'h00000a10;
  70
  71         // Defaults to compatibility with Micron N25Q/512MB and similar 3BA/4BA capable devices, with multicycle and write disabled
  72         // Note that the N25Q does not support normal reads in QSPI mode, so we leave the QSPI normal read commands equal
  73         // to the normal SPI commands for safety -- no corruption is possible if the device is latched into read mode...
  74         reg [31:0] flash_cfg1 = 32'h13031303;
  75         reg [31:0] flash_cfg2 = 32'heceb0c0b;
  76         reg [31:0] flash_cfg3 = 32'h34321202;
  77         reg [31:0] flash_cfg4 = 32'h00000000;
  78         reg [31:0] flash_cfg5 = 32'h00000000;
  79
  80         // Defaults to read mode
  81         reg [31:0] core_ctl1 = 32'h00000000;
  82         wire [31:0] core_data1;
  83
  84         // Device identifier
  85         assign device_id = 64'h7c5250545350494d;
  86         assign device_version = 32'h00010000;
  87
  88         reg cfg_wishbone_ack_reg = 0;
  89         reg [31:0] cfg_wishbone_dat_r_reg = 0;
  90
  91         assign cfg_wishbone_ack = cfg_wishbone_ack_reg;
  92         assign cfg_wishbone_dat_r = cfg_wishbone_dat_r_reg;
  93
  94         parameter WB_CFG_TRANSFER_STATE_IDLE = 0;
  95         parameter WB_CFG_TRANSFER_STATE_TR01 = 1;
  96
  97         reg [31:0] wishbone_config_buffer_address_reg = 0;
  98         reg [7:0] wishbone_config_transfer_state = 0;
  99         reg [31:0] wishbone_cfg_space_tx_buffer = 0;
 100         reg [31:0] wishbone_cfg_space_rx_buffer = 0;
 101
 102         // Wishbone configuration space connector
 103         always @(posedge peripheral_clock) begin
 104                 if (peripheral_reset) begin
 105                         // Reset Wishbone interface / control state machine
 106                         cfg_wishbone_ack_reg <= 0;
 107
 108                         wishbone_config_transfer_state <= WB_CFG_TRANSFER_STATE_IDLE;
 109                 end else begin
 110                         case (wishbone_config_transfer_state)
 111                                 WB_CFG_TRANSFER_STATE_IDLE: begin
 112                                         // Compute effective address
 113                                         wishbone_config_buffer_address_reg[31:2] = cfg_wishbone_adr;
 114                                         case (cfg_wishbone_sel)
 115                                                 4'b0001: wishbone_config_buffer_address_reg[1:0] = 0;
 116                                                 4'b0010: wishbone_config_buffer_address_reg[1:0] = 1;
 117                                                 4'b0100: wishbone_config_buffer_address_reg[1:0] = 2;
 118                                                 4'b1000: wishbone_config_buffer_address_reg[1:0] = 3;
 119                                                 4'b1111: wishbone_config_buffer_address_reg[1:0] = 0;
 120                                                 default: wishbone_config_buffer_address_reg[1:0] = 0;
 121                                         endcase
 122
 123                                         if (cfg_wishbone_cyc && cfg_wishbone_stb) begin
 124                                                 // Configuration register space access
 125                                                 // Single clock pulse signals in deasserted state...process incoming request!
 126                                                 if (!cfg_wishbone_we) begin
 127                                                         // Read requested
 128                                                         case ({wishbone_config_buffer_address_reg[7:2], 2'b00})
 129                                                                 0: wishbone_cfg_space_tx_buffer = device_id[63:32];
 130                                                                 4: wishbone_cfg_space_tx_buffer = device_id[31:0];
 131                                                                 8: wishbone_cfg_space_tx_buffer = device_version;
 132                                                                 12: wishbone_cfg_space_tx_buffer = sys_clk_freq;
 133                                                                 16: wishbone_cfg_space_tx_buffer = phy_cfg1;
 134                                                                 20: wishbone_cfg_space_tx_buffer = flash_cfg1;
 135                                                                 24: wishbone_cfg_space_tx_buffer = flash_cfg2;
 136                                                                 28: wishbone_cfg_space_tx_buffer = flash_cfg3;
 137                                                                 32: wishbone_cfg_space_tx_buffer = flash_cfg4;
 138                                                                 36: wishbone_cfg_space_tx_buffer = flash_cfg5;
 139                                                                 40: wishbone_cfg_space_tx_buffer = core_ctl1;
 140                                                                 44: wishbone_cfg_space_tx_buffer = core_data1;
 141                                                                 default: wishbone_cfg_space_tx_buffer = 0;
 142                                                         endcase
 143
 144                                                         // Endian swap
 145                                                         cfg_wishbone_dat_r_reg[31:24] <= wishbone_cfg_space_tx_buffer[7:0];
 146                                                         cfg_wishbone_dat_r_reg[23:16] <= wishbone_cfg_space_tx_buffer[15:8];
 147                                                         cfg_wishbone_dat_r_reg[15:8] <= wishbone_cfg_space_tx_buffer[23:16];
 148                                                         cfg_wishbone_dat_r_reg[7:0] <= wishbone_cfg_space_tx_buffer[31:24];
 149
 150                                                         // Signal transfer complete
 151                                                         cfg_wishbone_ack_reg <= 1;
 152
 153                                                         wishbone_config_transfer_state <= WB_CFG_TRANSFER_STATE_TR01;
 154                                                 end else begin
 155                                                         // Write requested
 156                                                         case ({wishbone_config_buffer_address_reg[7:2], 2'b00})
 157                                                                 // Device ID / version registers cannot be written, don't even try...
 158                                                                 16: wishbone_cfg_space_rx_buffer = phy_cfg1;
 159                                                                 20: wishbone_cfg_space_rx_buffer = flash_cfg1;
 160                                                                 24: wishbone_cfg_space_rx_buffer = flash_cfg2;
 161                                                                 28: wishbone_cfg_space_rx_buffer = flash_cfg3;
 162                                                                 32: wishbone_cfg_space_rx_buffer = flash_cfg4;
 163                                                                 36: wishbone_cfg_space_rx_buffer = flash_cfg5;
 164                                                                 40: wishbone_cfg_space_rx_buffer = core_ctl1;
 165                                                                 // Status registers cannot be written, don't even try...
 166                                                                 default: wishbone_cfg_space_rx_buffer = 0;
 167                                                         endcase
 168
 169                                                         if (cfg_wishbone_sel[0]) begin
 170                                                                 wishbone_cfg_space_rx_buffer[7:0] = cfg_wishbone_dat_w[31:24];
 171                                                         end
 172                                                         if (cfg_wishbone_sel[1]) begin
 173                                                                 wishbone_cfg_space_rx_buffer[15:8] = cfg_wishbone_dat_w[23:16];
 174                                                         end
 175                                                         if (cfg_wishbone_sel[2]) begin
 176                                                                 wishbone_cfg_space_rx_buffer[23:16] = cfg_wishbone_dat_w[15:8];
 177                                                         end
 178                                                         if (cfg_wishbone_sel[3]) begin
 179                                                                 wishbone_cfg_space_rx_buffer[31:24] = cfg_wishbone_dat_w[7:0];
 180                                                         end
 181
 182                                                         case ({wishbone_config_buffer_address_reg[7:2], 2'b00})
 183                                                                 16: phy_cfg1 <= wishbone_cfg_space_rx_buffer;
 184                                                                 20: flash_cfg1 <= wishbone_cfg_space_rx_buffer;
 185                                                                 24: flash_cfg2 <= wishbone_cfg_space_rx_buffer;
 186                                                                 28: flash_cfg3 <= wishbone_cfg_space_rx_buffer;
 187                                                                 32: flash_cfg4 <= wishbone_cfg_space_rx_buffer;
 188                                                                 36: flash_cfg5 <= wishbone_cfg_space_rx_buffer;
 189                                                                 40: core_ctl1 <= wishbone_cfg_space_rx_buffer;
 190                                                         endcase
 191
 192                                                         // Signal transfer complete
 193                                                         cfg_wishbone_ack_reg <= 1;
 194
 195                                                         wishbone_config_transfer_state <= WB_CFG_TRANSFER_STATE_TR01;
 196                                                 end
 197                                         end
 198                                 end
 199                                 WB_CFG_TRANSFER_STATE_TR01: begin
 200                                         // Cycle complete
 201                                         cfg_wishbone_ack_reg <= 0;
 202                                         wishbone_config_transfer_state <= WB_CFG_TRANSFER_STATE_IDLE;
 203                                 end
 204                                 default: begin
 205                                         // Should never reach this state
 206                                         wishbone_config_transfer_state <= WB_CFG_TRANSFER_STATE_IDLE;
 207                                 end
 208                         endcase
 209                 end
 210         end
 211
 212         // SPI bus signals
 213         wire spi_data_direction;
 214         wire spi_quad_mode_pin_enable;
 215         wire drive_host_interfaces;
 216         assign drive_host_interfaces = 1;
 217         assign spi_d_direction[0] = !spi_quad_mode_pin_enable || (spi_data_direction & drive_host_interfaces);
 218         assign spi_d_direction[1] = spi_quad_mode_pin_enable && (spi_data_direction & drive_host_interfaces);
 219         assign spi_d_direction[2] = !spi_quad_mode_pin_enable || (spi_data_direction & drive_host_interfaces);
 220         assign spi_d_direction[3] = !spi_quad_mode_pin_enable || (spi_data_direction & drive_host_interfaces);
 221
 222         // Interface registers
 223         wire [7:0] spi_clock_divisor;
 224         wire [7:0] dummy_cycle_count;
 225         wire [1:0] phy_io_type;
 226         wire [7:0] cs_extra_idle_cycles;
 227         wire four_byte_address_mode;
 228         wire fast_read_mode;
 229         wire qspi_read_quad_io_en;
 230         wire qspi_write_quad_io_en;
 231         wire [7:0] qspi_read_4ba_command_code;
 232         wire [7:0] qspi_read_3ba_command_code;
 233         wire [7:0] spi_read_4ba_command_code;
 234         wire [7:0] spi_read_3ba_command_code;
 235         wire [7:0] qspi_fast_read_4ba_command_code;
 236         wire [7:0] qspi_fast_read_3ba_command_code;
 237         wire [7:0] spi_fast_read_4ba_command_code;
 238         wire [7:0] spi_fast_read_3ba_command_code;
 239         wire [7:0] qspi_program_4ba_command_code;
 240         wire [7:0] qspi_program_3ba_command_code;
 241         wire [7:0] spi_program_4ba_command_code;
 242         wire [7:0] spi_program_3ba_command_code;
 243         wire [31:0] spi_cs_active_hold_cycles;
 244         wire allow_multicycle_writes;
 245         wire allow_multicycle_reads;
 246         wire user_command_mode;
 247         reg [7:0] user_command_mode_read_during_write = 0;
 248         assign spi_clock_divisor = phy_cfg1[7:0];
 249         assign dummy_cycle_count = phy_cfg1[15:8];
 250         assign phy_io_type = phy_cfg1[17:16];
 251         assign cs_extra_idle_cycles = phy_cfg1[31:24];
 252         assign four_byte_address_mode = phy_cfg1[18];
 253         assign fast_read_mode = phy_cfg1[19];
 254         assign qspi_read_quad_io_en = phy_cfg1[20];
 255         assign qspi_write_quad_io_en = phy_cfg1[21];
 256         assign qspi_read_4ba_command_code = flash_cfg1[31:24];
 257         assign qspi_read_3ba_command_code = flash_cfg1[23:16];
 258         assign spi_read_4ba_command_code = flash_cfg1[15:8];
 259         assign spi_read_3ba_command_code = flash_cfg1[7:0];
 260         assign qspi_fast_read_4ba_command_code = flash_cfg2[31:24];
 261         assign qspi_fast_read_3ba_command_code = flash_cfg2[23:16];
 262         assign spi_fast_read_4ba_command_code = flash_cfg2[15:8];
 263         assign spi_fast_read_3ba_command_code = flash_cfg2[7:0];
 264         assign qspi_program_4ba_command_code = flash_cfg3[31:24];
 265         assign qspi_program_3ba_command_code = flash_cfg3[23:16];
 266         assign spi_program_4ba_command_code = flash_cfg3[15:8];
 267         assign spi_program_3ba_command_code = flash_cfg3[7:0];
 268         assign spi_cs_active_hold_cycles = flash_cfg4[31:0];
 269         assign allow_multicycle_writes = flash_cfg5[1];
 270         assign allow_multicycle_reads = flash_cfg5[0];
 271         assign user_command_mode = core_ctl1[0];
 272         assign core_data1 = {24'h000000, user_command_mode_read_during_write};
 273
 274         parameter PHY_IO_TYPE_SINGLE = 0;
 275         parameter PHY_IO_TYPE_QUAD = 2;
 276
 277         // PHY clock generator
 278         // Divisor:
 279         // (spi_clock_divisor - 1) * 2
 280         // 0 == undefined (actually divide by two)
 281         // 1 == divide by 1
 282         // 2 == divide by 2
 283         // 3 == divide by 4
 284         // 4 == divide by 6
 285         // 5 == divide by 8
 286         // 6 == divide by 10
 287         // 7 == divide by 12
 288         // etc.
 289         wire spi_phy_clock;
 290         reg spi_phy_clock_gen_reg = 0;
 291         reg [7:0] spi_phy_clock_counter = 0;
 292         assign spi_phy_clock = (spi_clock_divisor == 1)?peripheral_clock:spi_phy_clock_gen_reg;
 293         always @(posedge peripheral_clock) begin
 294                 if (spi_phy_clock_counter >= (spi_clock_divisor - 2)) begin
 295                         spi_phy_clock_gen_reg <= ~spi_phy_clock_gen_reg;
 296                         spi_phy_clock_counter <= 0;
 297                 end else begin
 298                         spi_phy_clock_counter <= spi_phy_clock_counter + 1;
 299                 end
 300         end
 301
 302         reg [31:0] phy_tx_data = 0;
 303         wire [31:0] phy_rx_data;
 304         reg phy_hold_ss_active = 0;
 305         reg phy_qspi_mode_active = 0;
 306         reg phy_qspi_transfer_mode = 0;
 307         reg phy_qspi_transfer_direction = 0;
 308         reg [7:0] phy_dummy_cycle_count = 0;
 309         reg [3:0] single_cycle_read_counter = 0;
 310         reg [3:0] single_cycle_write_counter = 0;
 311         reg phy_cycle_start = 0;
 312         wire phy_transaction_complete;
 313
 314         spi_master_phy_quad spi_master_phy_quad(
 315                 .platform_clock(spi_phy_clock),
 316                 .reset(peripheral_reset),
 317                 .tx_data(phy_tx_data),
 318                 .rx_data(phy_rx_data),
 319                 .dummy_cycle_count(phy_dummy_cycle_count),
 320                 .hold_ss_active(phy_hold_ss_active),
 321                 .qspi_mode_active(phy_qspi_mode_active),
 322                 .qspi_transfer_mode(phy_qspi_transfer_mode),
 323                 .qspi_transfer_direction(phy_qspi_transfer_direction),
 324                 .cycle_start(phy_cycle_start),
 325                 .transaction_complete(phy_transaction_complete),
 326
 327                 .spi_clock(spi_clock),
 328                 .spi_d0_out(spi_d_out[0]),
 329                 .spi_d0_in(spi_d_in[0]),
 330                 .spi_d1_out(spi_d_out[1]),
 331                 .spi_d1_in(spi_d_in[1]),
 332                 .spi_d2_out(spi_d_out[2]),
 333                 .spi_d2_in(spi_d_in[2]),
 334                 .spi_d3_out(spi_d_out[3]),
 335                 .spi_d3_in(spi_d_in[3]),
 336                 .spi_ss_n(spi_ss_n),
 337                 .spi_data_direction(spi_data_direction),
 338                 .spi_quad_mode_pin_enable(spi_quad_mode_pin_enable)
 339         );
 340
 341         reg [3:0] wishbone_sel_reg = 0;
 342         reg wishbone_ack_reg = 0;
 343         assign wishbone_ack = wishbone_ack_reg;
 344         reg [31:0] wishbone_dat_r_reg = 0;
 345         assign wishbone_dat_r = wishbone_dat_r_reg;
 346
 347         parameter SPI_MASTER_TRANSFER_STATE_IDLE = 0;
 348         parameter SPI_MASTER_TRANSFER_STATE_TR01 = 1;
 349         parameter SPI_MASTER_TRANSFER_STATE_TR02 = 2;
 350         parameter SPI_MASTER_TRANSFER_STATE_TR03 = 16;
 351         parameter SPI_MASTER_TRANSFER_STATE_TR04 = 17;
 352         parameter SPI_MASTER_TRANSFER_STATE_TR05 = 18;
 353         parameter SPI_MASTER_TRANSFER_STATE_TR06 = 19;
 354         parameter SPI_MASTER_TRANSFER_STATE_TR07 = 20;
 355         parameter SPI_MASTER_TRANSFER_STATE_TR08 = 21;
 356         parameter SPI_MASTER_TRANSFER_STATE_TR09 = 22;
 357         parameter SPI_MASTER_TRANSFER_STATE_TR10 = 23;
 358         parameter SPI_MASTER_TRANSFER_STATE_TR11 = 24;
 359         parameter SPI_MASTER_TRANSFER_STATE_TR12 = 25;
 360         parameter SPI_MASTER_TRANSFER_STATE_RD01 = 32;
 361         parameter SPI_MASTER_TRANSFER_STATE_RD02 = 33;
 362         parameter SPI_MASTER_TRANSFER_STATE_RD03 = 34;
 363         parameter SPI_MASTER_TRANSFER_STATE_WR01 = 48;
 364         parameter SPI_MASTER_TRANSFER_STATE_WR02 = 49;
 365         parameter SPI_MASTER_TRANSFER_STATE_WR03 = 50;
 366         parameter SPI_MASTER_TRANSFER_STATE_UC01 = 64;
 367         parameter SPI_MASTER_TRANSFER_STATE_UC02 = 65;
 368         parameter SPI_MASTER_TRANSFER_STATE_UC03 = 66;
 369         parameter SPI_MASTER_TRANSFER_STATE_UC04 = 67;
 370
 371         reg [7:0] byte_out = 0;
 372         reg [7:0] spi_transfer_state = 0;
 373         reg spi_data_cycle_type = 0;
 374         reg [31:0] spi_address_reg = 0;
 375         reg [1:0] phy_io_type_reg;
 376         reg [31:0] spi_byte_read_count = 0;
 377         reg wishbone_data_cycle_type = 0;
 378         reg wishbone_access_is_32_bits = 0;
 379         reg user_command_mode_active = 0;
 380         reg multicycle_read_in_progress = 0;
 381         reg multicycle_write_in_progress = 0;
 382         reg [31:0] multicycle_transaction_address = 0;
 383         reg [7:0] cs_extra_cycle_counter = 0;
 384         reg [31:0] spi_cs_active_counter = 0;
 385
 386         assign debug_port = spi_transfer_state;
 387
 388         always @(posedge peripheral_clock) begin
 389                 if (peripheral_reset) begin
 390                         // Reset PHY
 391                         phy_hold_ss_active <= 0;
 392                         phy_qspi_mode_active <= 0;
 393                         phy_qspi_transfer_mode <= 0;
 394                         phy_qspi_transfer_direction <= 0;
 395                         phy_dummy_cycle_count <= 0;
 396                         phy_cycle_start <= 0;
 397
 398                         // Reset Wishbone interface / control state machine
 399                         wishbone_ack_reg <= 0;
 400                         wishbone_data_cycle_type <= 0;
 401                         wishbone_access_is_32_bits <= 0;
 402                         user_command_mode_read_during_write <= 0;
 403                         user_command_mode_active <= 0;
 404                         multicycle_read_in_progress <= 0;
 405                         multicycle_write_in_progress <= 0;
 406                         multicycle_transaction_address <= 0;
 407                         spi_cs_active_counter <= 0;
 408                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_IDLE;
 409                 end else begin
 410                         case (spi_transfer_state)
 411                                 SPI_MASTER_TRANSFER_STATE_IDLE: begin
 412                                         // Compute effective address
 413                                         spi_address_reg[31:2] = wishbone_adr;
 414                                         case (wishbone_sel)
 415                                                 4'b0001: spi_address_reg[1:0] = 0;
 416                                                 4'b0010: spi_address_reg[1:0] = 1;
 417                                                 4'b0100: spi_address_reg[1:0] = 2;
 418                                                 4'b1000: spi_address_reg[1:0] = 3;
 419                                                 4'b1111: spi_address_reg[1:0] = 0;
 420                                                 default: spi_address_reg[1:0] = 0;
 421                                         endcase
 422
 423                                         // Process command
 424                                         if ((spi_cs_active_hold_cycles > 0) && (spi_cs_active_counter >= spi_cs_active_hold_cycles)) begin
 425                                                 // Stop multicycle transfer
 426                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 427                                         end else if (!user_command_mode && user_command_mode_active) begin
 428                                                 // Exit user command mode
 429                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 430                                         end else if (multicycle_read_in_progress) begin
 431                                                 if (!allow_multicycle_reads) begin
 432                                                         // Stop multicycle transfer
 433                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 434                                                 end else if (wishbone_cyc && wishbone_stb) begin
 435                                                         if (user_command_mode) begin
 436                                                                 // User command mode requested
 437                                                                 // Stop multicycle transfer in preparation to enable user command mode
 438                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 439                                                         end else if (wishbone_data_cycle_type) begin
 440                                                                 // Write requested
 441                                                                 // Stop multicycle transfer in preparation to enable write mode
 442                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 443                                                         end else begin
 444                                                                 // Select 8-bit/32-bit transfer size via Wishbone access mode
 445                                                                 if (wishbone_sel == 4'b1111) begin
 446                                                                         wishbone_access_is_32_bits <= 1;
 447                                                                 end else begin
 448                                                                         wishbone_access_is_32_bits <= 0;
 449                                                                 end
 450                                                                 wishbone_sel_reg <= wishbone_sel;
 451
 452                                                                 // Verify next address matches current address
 453                                                                 if (four_byte_address_mode) begin
 454                                                                         if (multicycle_transaction_address == spi_address_reg) begin
 455                                                                                 // Transfer next data chunk
 456                                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_RD01;
 457                                                                         end else begin
 458                                                                                 // Stop multicycle transfer
 459                                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 460                                                                         end
 461                                                                 end else begin
 462                                                                         if (multicycle_transaction_address[23:0] == spi_address_reg[23:0]) begin
 463                                                                                 // Transfer next data chunk
 464                                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_RD01;
 465                                                                         end else begin
 466                                                                                 // Stop multicycle transfer
 467                                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 468                                                                         end
 469                                                                 end
 470                                                         end
 471                                                 end
 472                                         end else if (multicycle_write_in_progress) begin
 473                                                 if (!allow_multicycle_writes) begin
 474                                                         // Stop multicycle transfer
 475                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 476                                                 end else if (wishbone_cyc && wishbone_stb) begin
 477                                                         if (user_command_mode) begin
 478                                                                 // User command mode requested
 479                                                                 // Stop multicycle transfer in preparation to enable user command mode
 480                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 481                                                         end else if (!wishbone_data_cycle_type) begin
 482                                                                 // Read requested
 483                                                                 // Stop multicycle transfer in preparation to enable read mode
 484                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 485                                                         end else begin
 486                                                                 // Select 8-bit/32-bit transfer size via Wishbone access mode
 487                                                                 if (wishbone_sel == 4'b1111) begin
 488                                                                         wishbone_access_is_32_bits <= 1;
 489                                                                 end else begin
 490                                                                         wishbone_access_is_32_bits <= 0;
 491                                                                 end
 492                                                                 wishbone_sel_reg <= wishbone_sel;
 493
 494                                                                 // Verify next address matches current address
 495                                                                 if (four_byte_address_mode) begin
 496                                                                         if (multicycle_transaction_address == spi_address_reg) begin
 497                                                                                 // Transfer next data chunk
 498                                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_WR01;
 499                                                                         end else begin
 500                                                                                 // Stop multicycle transfer
 501                                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 502                                                                         end
 503                                                                 end else begin
 504                                                                         if (multicycle_transaction_address[23:0] == spi_address_reg[23:0]) begin
 505                                                                                 // Transfer next data chunk
 506                                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_WR01;
 507                                                                         end else begin
 508                                                                                 // Stop multicycle transfer
 509                                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 510                                                                         end
 511                                                                 end
 512                                                         end
 513                                                 end
 514                                         end else begin
 515                                                 if (wishbone_cyc && wishbone_stb) begin
 516                                                         if (wishbone_sel == 4'b1111) begin
 517                                                                 wishbone_access_is_32_bits <= 1;
 518                                                         end else begin
 519                                                                 wishbone_access_is_32_bits <= 0;
 520                                                         end
 521                                                         wishbone_sel_reg <= wishbone_sel;
 522                                                         wishbone_data_cycle_type <= wishbone_we;
 523                                                         phy_io_type_reg <= phy_io_type;
 524                                                         if (!phy_transaction_complete) begin
 525                                                                 if (user_command_mode) begin
 526                                                                         // Read the data byte to write from the active lane
 527                                                                         if (wishbone_sel[0]) begin
 528                                                                                 phy_tx_data[7:0] <= wishbone_dat_w[31:24];
 529                                                                         end else if (wishbone_sel[1]) begin
 530                                                                                 phy_tx_data[7:0] <= wishbone_dat_w[23:16];
 531                                                                         end else if (wishbone_sel[2]) begin
 532                                                                                 phy_tx_data[7:0] <= wishbone_dat_w[15:8];
 533                                                                         end else if (wishbone_sel[3]) begin
 534                                                                                 phy_tx_data[7:0] <= wishbone_dat_w[7:0];
 535                                                                         end else begin
 536                                                                                 phy_tx_data[7:0] = 8'hff;       // Safe default -- will not send any useful commands / data
 537                                                                         end
 538
 539                                                                         // Set up SPI access
 540                                                                         phy_tx_data[31:8] = 0;
 541                                                                         phy_qspi_mode_active <= 0;
 542                                                                         phy_qspi_transfer_mode <= 0;
 543                                                                         phy_dummy_cycle_count <= 0;
 544                                                                         phy_hold_ss_active <= 1;
 545                                                                         phy_cycle_start <= 1;
 546
 547                                                                         // Set user command mode active
 548                                                                         user_command_mode_active <= 1;
 549                                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC01;
 550                                                                 end else begin
 551                                                                         if (!wishbone_we) begin
 552                                                                                 // Set up SPI read access
 553                                                                                 if (phy_io_type == PHY_IO_TYPE_QUAD) begin
 554                                                                                         if (four_byte_address_mode) begin
 555                                                                                                 if (fast_read_mode) begin
 556                                                                                                         phy_tx_data <= qspi_fast_read_4ba_command_code;
 557                                                                                                 end else begin
 558                                                                                                         phy_tx_data <= qspi_read_4ba_command_code;
 559                                                                                                 end
 560                                                                                         end else begin
 561                                                                                                 if (fast_read_mode) begin
 562                                                                                                         phy_tx_data <= qspi_fast_read_3ba_command_code;
 563                                                                                                 end else begin
 564                                                                                                         phy_tx_data <= qspi_read_3ba_command_code;
 565                                                                                                 end
 566                                                                                         end
 567                                                                                 end else begin
 568                                                                                         if (four_byte_address_mode) begin
 569                                                                                                 if (fast_read_mode) begin
 570                                                                                                         phy_tx_data <= spi_fast_read_4ba_command_code;
 571                                                                                                 end else begin
 572                                                                                                         phy_tx_data <= spi_read_4ba_command_code;
 573                                                                                                 end
 574                                                                                         end else begin
 575                                                                                                 if (fast_read_mode) begin
 576                                                                                                         phy_tx_data <= spi_fast_read_3ba_command_code;
 577                                                                                                 end else begin
 578                                                                                                         phy_tx_data <= spi_read_3ba_command_code;
 579                                                                                                 end
 580                                                                                         end
 581                                                                                 end
 582                                                                                 if (allow_multicycle_reads) begin
 583                                                                                         multicycle_read_in_progress <= 1;
 584                                                                                 end else begin
 585                                                                                         single_cycle_read_counter <= 0;
 586                                                                                 end
 587                                                                         end else begin
 588                                                                                 // Set up SPI write access
 589                                                                                 if (phy_io_type == PHY_IO_TYPE_QUAD) begin
 590                                                                                         if (four_byte_address_mode) begin
 591                                                                                                 phy_tx_data <= qspi_program_4ba_command_code;
 592                                                                                         end else begin
 593                                                                                                 phy_tx_data <= qspi_program_3ba_command_code;
 594                                                                                         end
 595                                                                                 end else begin
 596                                                                                         if (four_byte_address_mode) begin
 597                                                                                                 phy_tx_data <= spi_program_4ba_command_code;
 598                                                                                         end else begin
 599                                                                                                 phy_tx_data <= spi_program_3ba_command_code;
 600                                                                                         end
 601                                                                                 end
 602                                                                                 if (allow_multicycle_writes) begin
 603                                                                                         multicycle_write_in_progress <= 1;
 604                                                                                 end else begin
 605                                                                                         single_cycle_write_counter <= 0;
 606                                                                                 end
 607                                                                         end
 608                                                                         phy_qspi_mode_active <= 0;
 609                                                                         phy_qspi_transfer_mode <= 0;
 610                                                                         phy_dummy_cycle_count <= 0;
 611                                                                         phy_hold_ss_active <= 1;
 612                                                                         phy_cycle_start <= 1;
 613
 614                                                                         if (four_byte_address_mode) begin
 615                                                                                 multicycle_transaction_address <= spi_address_reg;
 616                                                                         end else begin
 617                                                                                 multicycle_transaction_address <= {8'h00, spi_address_reg[23:0]};
 618                                                                         end
 619
 620                                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR03;
 621                                                                 end
 622                                                         end
 623                                                 end
 624                                         end
 625
 626                                         if ((spi_cs_active_hold_cycles > 0) && (multicycle_read_in_progress || multicycle_write_in_progress)) begin
 627                                                 spi_cs_active_counter <= spi_cs_active_counter + 1;
 628                                         end else begin
 629                                                 spi_cs_active_counter <= 0;
 630                                         end
 631                                 end
 632                                 SPI_MASTER_TRANSFER_STATE_UC01: begin
 633                                         if (phy_transaction_complete) begin
 634                                                 phy_cycle_start <= 0;
 635
 636                                                 user_command_mode_read_during_write <= phy_rx_data[7:0];
 637                                                 if (!wishbone_data_cycle_type) begin
 638                                                         // Read cycle
 639                                                         // Replicate the output bytes to all active lanes
 640                                                         if (wishbone_sel_reg[0]) begin
 641                                                                 wishbone_dat_r_reg[31:24] <= phy_rx_data[7:0];
 642                                                         end
 643                                                         if (wishbone_sel_reg[1]) begin
 644                                                                 wishbone_dat_r_reg[23:16] <= phy_rx_data[7:0];
 645                                                         end
 646                                                         if (wishbone_sel_reg[2]) begin
 647                                                                 wishbone_dat_r_reg[15:8] <= phy_rx_data[7:0];
 648                                                         end
 649                                                         if (wishbone_sel_reg[3]) begin
 650                                                                 wishbone_dat_r_reg[7:0] <= phy_rx_data[7:0];
 651                                                         end
 652                                                 end
 653
 654                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR01;
 655                                         end
 656                                 end
 657                                 SPI_MASTER_TRANSFER_STATE_UC02: begin
 658                                         // Release CS and prepare the SPI device for the next command
 659                                         phy_hold_ss_active <= 0;
 660                                         phy_qspi_transfer_mode <= 0;
 661                                         phy_qspi_mode_active <= 0;
 662
 663                                         // Terminate user command mode / multicycle transfers
 664                                         user_command_mode_active <= 0;
 665                                         multicycle_read_in_progress <= 0;
 666                                         multicycle_write_in_progress <= 0;
 667                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC03;
 668                                 end
 669                                 SPI_MASTER_TRANSFER_STATE_UC03: begin
 670                                         // Wait for CS to return to idle, since this state machine is running
 671                                         // significantly faster than the SPI PHY state machine.  This avoids
 672                                         // potentially short cycling the PHY and not allowing CS to return
 673                                         // to idle, thus inadvertently chaining the next command onto the
 674                                         // previous one!
 675                                         if (spi_ss_n) begin
 676                                                 if (cs_extra_idle_cycles > 0) begin
 677                                                         cs_extra_cycle_counter <= 1;
 678                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC04;
 679                                                 end else begin
 680                                                         // Return to idle
 681                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_IDLE;
 682                                                 end
 683                                         end
 684                                 end
 685                                 SPI_MASTER_TRANSFER_STATE_UC04: begin
 686                                         if (cs_extra_cycle_counter >= cs_extra_idle_cycles) begin
 687                                                 // Return to idle
 688                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_IDLE;
 689                                         end else begin
 690                                                 cs_extra_cycle_counter <= cs_extra_cycle_counter + 1;
 691                                         end
 692                                 end
 693                                 SPI_MASTER_TRANSFER_STATE_TR01: begin
 694                                         // Wait for CS to return to idle, since this state machine is running
 695                                         // significantly faster than the SPI PHY state machine.  This avoids
 696                                         // potentially short cycling the PHY and not allowing CS to return
 697                                         // to idle, thus inadvertently chaining the next command onto the
 698                                         // previous one!
 699                                         // If user command mode is active, CS will be asserted by design,
 700                                         // so ignore...
 701                                         if (spi_ss_n || user_command_mode_active
 702                                                 || multicycle_read_in_progress
 703                                                 || multicycle_write_in_progress) begin
 704                                                 if (!wishbone_data_cycle_type
 705                                                         && wishbone_access_is_32_bits
 706                                                         && !allow_multicycle_reads
 707                                                         && (single_cycle_read_counter < 4)) begin
 708                                                         // Set up SPI read access for next byte
 709                                                         if (phy_io_type == PHY_IO_TYPE_QUAD) begin
 710                                                                 if (four_byte_address_mode) begin
 711                                                                         if (fast_read_mode) begin
 712                                                                                 phy_tx_data <= qspi_fast_read_4ba_command_code;
 713                                                                         end else begin
 714                                                                                 phy_tx_data <= qspi_read_4ba_command_code;
 715                                                                         end
 716                                                                 end else begin
 717                                                                         if (fast_read_mode) begin
 718                                                                                 phy_tx_data <= qspi_fast_read_3ba_command_code;
 719                                                                         end else begin
 720                                                                                 phy_tx_data <= qspi_read_3ba_command_code;
 721                                                                         end
 722                                                                 end
 723                                                         end else begin
 724                                                                 if (four_byte_address_mode) begin
 725                                                                         if (fast_read_mode) begin
 726                                                                                 phy_tx_data <= spi_fast_read_4ba_command_code;
 727                                                                         end else begin
 728                                                                                 phy_tx_data <= spi_read_4ba_command_code;
 729                                                                         end
 730                                                                 end else begin
 731                                                                         if (fast_read_mode) begin
 732                                                                                 phy_tx_data <= spi_fast_read_3ba_command_code;
 733                                                                         end else begin
 734                                                                                 phy_tx_data <= spi_read_3ba_command_code;
 735                                                                         end
 736                                                                 end
 737                                                         end
 738
 739                                                         phy_qspi_mode_active <= 0;
 740                                                         phy_qspi_transfer_mode <= 0;
 741                                                         phy_dummy_cycle_count <= 0;
 742                                                         phy_hold_ss_active <= 1;
 743                                                         phy_cycle_start <= 1;
 744
 745                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR03;
 746                                                 end else if (wishbone_data_cycle_type
 747                                                         && wishbone_access_is_32_bits
 748                                                         && !allow_multicycle_writes
 749                                                         && (single_cycle_write_counter < 4)) begin
 750                                                         // Set up SPI write access for next byte
 751                                                         if (phy_io_type == PHY_IO_TYPE_QUAD) begin
 752                                                                 if (four_byte_address_mode) begin
 753                                                                         phy_tx_data <= qspi_program_4ba_command_code;
 754                                                                 end else begin
 755                                                                         phy_tx_data <= qspi_program_3ba_command_code;
 756                                                                 end
 757                                                         end else begin
 758                                                                 if (four_byte_address_mode) begin
 759                                                                         phy_tx_data <= spi_program_4ba_command_code;
 760                                                                 end else begin
 761                                                                         phy_tx_data <= spi_program_3ba_command_code;
 762                                                                 end
 763                                                         end
 764
 765                                                         phy_qspi_mode_active <= 0;
 766                                                         phy_qspi_transfer_mode <= 0;
 767                                                         phy_dummy_cycle_count <= 0;
 768                                                         phy_hold_ss_active <= 1;
 769                                                         phy_cycle_start <= 1;
 770
 771                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR03;
 772                                                 end else begin
 773                                                         // Signal transfer complete
 774                                                         wishbone_ack_reg <= 1;
 775
 776                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR02;
 777                                                 end
 778                                         end
 779                                 end
 780                                 SPI_MASTER_TRANSFER_STATE_TR02: begin
 781                                         // Cycle complete
 782                                         wishbone_ack_reg <= 0;
 783                                         spi_cs_active_counter <= 0;
 784                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_IDLE;
 785                                 end
 786                                 SPI_MASTER_TRANSFER_STATE_TR03: begin
 787                                         if (phy_transaction_complete) begin
 788                                                 phy_cycle_start <= 0;
 789                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR04;
 790                                         end
 791                                 end
 792                                 SPI_MASTER_TRANSFER_STATE_TR04: begin
 793                                         if (phy_io_type_reg == PHY_IO_TYPE_QUAD) begin
 794                                                 if (!wishbone_data_cycle_type) begin
 795                                                         // Read
 796                                                         phy_qspi_mode_active <= qspi_read_quad_io_en;
 797                                                 end else begin
 798                                                         // Write
 799                                                         phy_qspi_mode_active <= qspi_write_quad_io_en;
 800                                                 end
 801                                         end else begin
 802                                                 phy_qspi_mode_active <= 0;
 803                                         end
 804                                         if (four_byte_address_mode) begin
 805                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR05;
 806                                         end else begin
 807                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR07;
 808                                         end
 809                                 end
 810                                 SPI_MASTER_TRANSFER_STATE_TR05: begin
 811                                         // Address (4 bytes / 1 word)
 812                                         if (!phy_transaction_complete) begin
 813                                                 if (wishbone_access_is_32_bits && !allow_multicycle_reads) begin
 814                                                         phy_tx_data <= multicycle_transaction_address;
 815                                                 end else begin
 816                                                         phy_tx_data <= spi_address_reg;
 817                                                 end
 818                                                 phy_qspi_transfer_mode <= 1;
 819                                                 phy_qspi_transfer_direction <= 1;
 820                                                 if (!wishbone_data_cycle_type) begin
 821                                                         // Read
 822                                                         if (fast_read_mode) begin
 823                                                                 phy_dummy_cycle_count <= dummy_cycle_count;
 824                                                         end else begin
 825                                                                 phy_dummy_cycle_count <= 0;
 826                                                         end
 827                                                 end else begin
 828                                                         // Write
 829                                                         phy_dummy_cycle_count <= 0;
 830                                                 end
 831                                                 phy_cycle_start <= 1;
 832
 833                                                 spi_byte_read_count <= 0;
 834                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR06;
 835                                         end
 836                                 end
 837                                 SPI_MASTER_TRANSFER_STATE_TR06: begin
 838                                         if (phy_transaction_complete) begin
 839                                                 phy_cycle_start <= 0;
 840
 841                                                 if (phy_io_type_reg == PHY_IO_TYPE_QUAD) begin
 842                                                         phy_qspi_mode_active <= 1;
 843                                                 end else begin
 844                                                         phy_qspi_mode_active <= 0;
 845                                                 end
 846
 847                                                 if (wishbone_data_cycle_type) begin
 848                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_WR01;
 849                                                 end else begin
 850                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_RD01;
 851                                                 end
 852                                         end
 853                                 end
 854                                 SPI_MASTER_TRANSFER_STATE_RD01: begin
 855                                         if (!phy_transaction_complete) begin
 856                                                 // Data words
 857                                                 phy_tx_data <= 0;       // Not used
 858                                                 if (phy_io_type_reg == PHY_IO_TYPE_QUAD) begin
 859                                                         phy_qspi_mode_active <= 1;
 860                                                 end else begin
 861                                                         phy_qspi_mode_active <= 0;
 862                                                 end
 863                                                 if (wishbone_access_is_32_bits && allow_multicycle_reads) begin
 864                                                         phy_qspi_transfer_mode <= 1;
 865                                                 end else begin
 866                                                         phy_qspi_transfer_mode <= 0;
 867                                                 end
 868                                                 phy_qspi_transfer_direction <= 0;
 869                                                 phy_dummy_cycle_count <= 0;
 870                                                 phy_cycle_start <= 1;
 871                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_RD02;
 872                                         end
 873                                 end
 874                                 SPI_MASTER_TRANSFER_STATE_RD02: begin
 875                                         if (phy_transaction_complete) begin
 876                                                 // Set Wishbone output data
 877                                                 if (wishbone_access_is_32_bits) begin
 878                                                         if (allow_multicycle_reads) begin
 879                                                                 wishbone_dat_r_reg <= phy_rx_data;
 880                                                                 multicycle_transaction_address <= multicycle_transaction_address + 4;
 881                                                         end else begin
 882                                                                 if (single_cycle_read_counter == 0) begin
 883                                                                         wishbone_dat_r_reg[31:24] <= phy_rx_data[7:0];
 884                                                                 end else if (single_cycle_read_counter == 1) begin
 885                                                                         wishbone_dat_r_reg[23:16] <= phy_rx_data[7:0];
 886                                                                 end else if (single_cycle_read_counter == 2) begin
 887                                                                         wishbone_dat_r_reg[15:8] <= phy_rx_data[7:0];
 888                                                                 end else if (single_cycle_read_counter == 3) begin
 889                                                                         wishbone_dat_r_reg[7:0] <= phy_rx_data[7:0];
 890                                                                 end
 891                                                                 single_cycle_read_counter <= single_cycle_read_counter + 1;
 892                                                                 multicycle_transaction_address <= multicycle_transaction_address + 1;
 893                                                         end
 894                                                 end else begin
 895                                                         // Replicate the data bytes to all active lanes
 896                                                         if (wishbone_sel_reg[0]) begin
 897                                                                 wishbone_dat_r_reg[31:24] <= phy_rx_data[7:0];
 898                                                         end
 899                                                         if (wishbone_sel_reg[1]) begin
 900                                                                 wishbone_dat_r_reg[23:16] <= phy_rx_data[7:0];
 901                                                         end
 902                                                         if (wishbone_sel_reg[2]) begin
 903                                                                 wishbone_dat_r_reg[15:8] <= phy_rx_data[7:0];
 904                                                         end
 905                                                         if (wishbone_sel_reg[3]) begin
 906                                                                 wishbone_dat_r_reg[7:0] <= phy_rx_data[7:0];
 907                                                         end
 908                                                         multicycle_transaction_address <= multicycle_transaction_address + 1;
 909                                                 end
 910
 911                                                 phy_cycle_start <= 0;
 912                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_RD03;
 913                                         end
 914                                 end
 915                                 SPI_MASTER_TRANSFER_STATE_RD03: begin
 916                                         if (!phy_transaction_complete) begin
 917                                                 // Release CS (if required)
 918                                                 if (!multicycle_read_in_progress) begin
 919                                                         phy_hold_ss_active <= 0;
 920                                                 end
 921
 922                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR01;
 923                                         end
 924                                 end
 925                                 SPI_MASTER_TRANSFER_STATE_WR01: begin
 926                                         if (!phy_transaction_complete) begin
 927                                                 // Data words
 928                                                 if (wishbone_access_is_32_bits) begin
 929                                                         if (allow_multicycle_writes) begin
 930                                                                 phy_tx_data <= wishbone_dat_w;
 931                                                                 phy_qspi_transfer_mode <= 1;
 932                                                                 multicycle_transaction_address <= multicycle_transaction_address + 4;
 933                                                         end else begin
 934                                                                 if (single_cycle_write_counter == 0) begin
 935                                                                         phy_tx_data[7:0] <= wishbone_dat_w[7:0];
 936                                                                 end else if (single_cycle_write_counter == 1) begin
 937                                                                         phy_tx_data[7:0] <= wishbone_dat_w[15:8];
 938                                                                 end else if (single_cycle_write_counter == 2) begin
 939                                                                         phy_tx_data[7:0] <= wishbone_dat_w[23:16];
 940                                                                 end else if (single_cycle_write_counter == 3) begin
 941                                                                         phy_tx_data[7:0] <= wishbone_dat_w[31:24];
 942                                                                 end
 943                                                                 phy_qspi_transfer_mode <= 0;
 944                                                                 single_cycle_write_counter <= single_cycle_write_counter + 1;
 945                                                                 multicycle_transaction_address <= multicycle_transaction_address + 1;
 946                                                         end
 947                                                 end else begin
 948                                                         // Write cycle
 949                                                         // Read the data byte to write from the active lane
 950                                                         if (wishbone_sel_reg[0]) begin
 951                                                                 phy_tx_data[7:0] <= wishbone_dat_w[31:24];
 952                                                         end else if (wishbone_sel_reg[1]) begin
 953                                                                 phy_tx_data[7:0] <= wishbone_dat_w[23:16];
 954                                                         end else if (wishbone_sel_reg[2]) begin
 955                                                                 phy_tx_data[7:0] <= wishbone_dat_w[15:8];
 956                                                         end else if (wishbone_sel_reg[3]) begin
 957                                                                 phy_tx_data[7:0] <= wishbone_dat_w[7:0];
 958                                                         end else begin
 959                                                                 phy_tx_data[7:0] = 8'hff;       // Safe default -- will not overwrite any bits
 960                                                         end
 961                                                         phy_tx_data[31:8] = 0;
 962                                                         phy_qspi_transfer_mode <= 0;
 963                                                         multicycle_transaction_address <= multicycle_transaction_address + 1;
 964                                                 end
 965                                                 if (phy_io_type_reg == PHY_IO_TYPE_QUAD) begin
 966                                                         phy_qspi_mode_active <= 1;
 967                                                 end else begin
 968                                                         phy_qspi_mode_active <= 0;
 969                                                 end
 970                                                 phy_qspi_transfer_direction <= 1;
 971                                                 phy_dummy_cycle_count <= 0;
 972                                                 phy_cycle_start <= 1;
 973                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_WR02;
 974                                         end
 975                                 end
 976                                 SPI_MASTER_TRANSFER_STATE_WR02: begin
 977                                         if (phy_transaction_complete) begin
 978                                                 phy_cycle_start <= 0;
 979
 980                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_WR03;
 981                                         end
 982                                 end
 983                                 SPI_MASTER_TRANSFER_STATE_WR03: begin
 984                                         if (!phy_transaction_complete) begin
 985                                                 // Release CS (if required)
 986                                                 if (!multicycle_write_in_progress) begin
 987                                                         phy_hold_ss_active <= 0;
 988                                                 end
 989
 990                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR01;
 991                                         end
 992                                 end
 993                                 SPI_MASTER_TRANSFER_STATE_TR07: begin
 994                                         // Send the three address bytes one at a time...
 995                                         if (!phy_transaction_complete) begin
 996                                                 if (wishbone_access_is_32_bits && !allow_multicycle_reads) begin
 997                                                         phy_tx_data <= multicycle_transaction_address[23:16];
 998                                                 end else begin
 999                                                         phy_tx_data <= spi_address_reg[23:16];
1000                                                 end
1001                                                 if (phy_io_type_reg == PHY_IO_TYPE_QUAD) begin
1002                                                         phy_qspi_mode_active <= 1;
1003                                                 end else begin
1004                                                         phy_qspi_mode_active <= 0;
1005                                                 end
1006                                                 phy_qspi_transfer_mode <= 0;
1007                                                 phy_qspi_transfer_direction <= 1;
1008                                                 phy_dummy_cycle_count <= 0;
1009                                                 phy_cycle_start <= 1;
1010
1011                                                 spi_byte_read_count <= 0;
1012                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR08;
1013                                         end
1014                                 end
1015                                 SPI_MASTER_TRANSFER_STATE_TR08: begin
1016                                         if (phy_transaction_complete) begin
1017                                                 phy_cycle_start <= 0;
1018                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR09;
1019                                         end
1020                                 end
1021                                 SPI_MASTER_TRANSFER_STATE_TR09: begin
1022                                         if (!phy_transaction_complete) begin
1023                                                 if (wishbone_access_is_32_bits && !allow_multicycle_reads) begin
1024                                                         phy_tx_data <= multicycle_transaction_address[15:8];
1025                                                 end else begin
1026                                                         phy_tx_data <= spi_address_reg[15:8];
1027                                                 end
1028                                                 if (phy_io_type_reg == PHY_IO_TYPE_QUAD) begin
1029                                                         phy_qspi_mode_active <= 1;
1030                                                 end else begin
1031                                                         phy_qspi_mode_active <= 0;
1032                                                 end
1033                                                 phy_qspi_transfer_mode <= 0;
1034                                                 phy_qspi_transfer_direction <= 1;
1035                                                 phy_dummy_cycle_count <= 0;
1036                                                 phy_cycle_start <= 1;
1037
1038                                                 spi_byte_read_count <= 0;
1039                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR10;
1040                                         end
1041                                 end
1042                                 SPI_MASTER_TRANSFER_STATE_TR10: begin
1043                                         if (phy_transaction_complete) begin
1044                                                 phy_cycle_start <= 0;
1045                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR11;
1046                                         end
1047                                 end
1048                                 SPI_MASTER_TRANSFER_STATE_TR11: begin
1049                                         if (!phy_transaction_complete) begin
1050                                                 if (wishbone_access_is_32_bits && !allow_multicycle_reads) begin
1051                                                         phy_tx_data <= multicycle_transaction_address[7:0];
1052                                                 end else begin
1053                                                         phy_tx_data <= spi_address_reg[7:0];
1054                                                 end
1055                                                 if (phy_io_type_reg == PHY_IO_TYPE_QUAD) begin
1056                                                         phy_qspi_mode_active <= 1;
1057                                                 end else begin
1058                                                         phy_qspi_mode_active <= 0;
1059                                                 end
1060                                                 phy_qspi_transfer_mode <= 0;
1061                                                 phy_qspi_transfer_direction <= 1;
1062                                                 if (!wishbone_data_cycle_type) begin
1063                                                         // Read
1064                                                         if (fast_read_mode) begin
1065                                                                 phy_dummy_cycle_count <= dummy_cycle_count;
1066                                                         end else begin
1067                                                                 phy_dummy_cycle_count <= 0;
1068                                                         end
1069                                                 end else begin
1070                                                         phy_dummy_cycle_count <= 0;
1071                                                 end
1072                                                 phy_cycle_start <= 1;
1073
1074                                                 spi_byte_read_count <= 0;
1075                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR12;
1076                                         end
1077                                 end
1078                                 SPI_MASTER_TRANSFER_STATE_TR12: begin
1079                                         if (phy_transaction_complete) begin
1080                                                 phy_cycle_start <= 0;
1081                                                 if (wishbone_data_cycle_type) begin
1082                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_WR01;
1083                                                 end else begin
1084                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_RD01;
1085                                                 end
1086                                         end
1087                                 end
1088                                 default: begin
1089                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_IDLE;
1090                                 end
1091                         endcase
1092                 end
1093         end
1094 endmodule