Add initial Tercel support for Arctic Tern
[microwatt.git] / soc.vhdl
2022-02-23 Raptor Engineering... Add initial Tercel support for Arctic Tern
2021-03-24 Anton BlanchardMerge pull request #285 from antonblanchard/Makefile...
2021-03-24 Anton BlanchardMerge pull request #281 from antonblanchard/cache-tlb...
2021-03-23 Anton BlanchardMerge pull request #284 from antonblanchard/boot-clocks
2021-03-15 Anton BlanchardAllow SPI BOOT_CLOCKS to be overridden by top level
2021-03-15 Anton BlanchardPass icache/dcache/tlb parameters down from soc
2021-02-08 Michael NeulingMerge pull request #269 from paulusmack/pipeline
2021-02-08 Michael NeulingMerge pull request #268 from paulusmack/btc
2021-02-08 Michael NeulingMerge pull request #273 from antonblanchard/wishbone...
2021-02-08 Anton BlanchardAdd some wishbone checking
2021-01-18 Paul Mackerrasfetch1: Implement a simple branch target cache
2021-01-07 Paul MackerrasMerge pull request #259 from antonblanchard/dmi-reset
2020-12-21 Anton BlanchardMerge pull request #261 from antonblanchard/wishbone_layout
2020-12-21 Anton BlanchardMerge pull request #260 from paulusmack/misc
2020-12-17 Paul Mackerrassoc: Drive uart1_irq to 0 when we don't have UART1
2020-09-17 Michael NeulingMerge pull request #245 from paulusmack/fpu
2020-09-03 Paul Mackerrascore: Add support for floating-point loads and stores
2020-06-30 Paul MackerrasMerge pull request #206 from Jbalkind/icachecleanup
2020-06-29 Michael NeulingMerge pull request #213 from ozbenh/uart16550
2020-06-29 Michael NeulingMerge pull request #212 from ozbenh/liteeth
2020-06-25 Benjamin Herrenschmidtuart: Make 16550 the default
2020-06-23 Benjamin Herrenschmidtuart: Import and hook up opencore 16550 compatible...
2020-06-23 Benjamin Herrenschmidtliteeth: Hook up LiteX LiteEth ethernet controller
2020-06-23 Michael NeulingMerge pull request #210 from ozbenh/xics
2020-06-22 Benjamin Herrenschmidtxics: Add support for reduced priority field size
2020-06-19 Benjamin Herrenschmidtxics: Add simple ICS
2020-06-19 Michael NeulingMerge pull request #208 from paulusmack/faster
2020-06-17 Paul MackerrasMerge pull request #207 from ozbenh/misc
2020-06-16 Paul MackerrasMake LOG_LENGTH configurable per FPGA variant
2020-06-14 Benjamin Herrenschmidtsoc: Slight cleanup of IRQ assignments
2020-06-14 Benjamin Herrenschmidtsoc: Rename uart_dat8 to uart0_dat8
2020-06-14 Benjamin Herrenschmidtsoc: Rename wb_dram_ctrl to wb_ext_io and rework decoding
2020-06-13 Benjamin Herrenschmidtsoc: Don't require dram wishbones signals to be wired...
2020-06-13 Benjamin Herrenschmidtsoc: Add defaults for some input signals
2020-06-13 Benjamin Herrenschmidtsoc: Remove unused RESET_LOW generic
2020-06-13 Paul MackerrasMerge pull request #205 from ozbenh/timing
2020-06-13 Paul MackerrasMerge pull request #204 from ozbenh/spi
2020-06-13 Benjamin Herrenschmidtbram: Remove combinational loop on stall
2020-06-13 Benjamin Herrenschmidtuart: Remove combinational loops on ack and stall signal
2020-06-12 Benjamin Herrenschmidtspi: Add SPI Flash controller
2020-06-05 Paul MackerrasMerge pull request #191 from ozbenh/litedram
2020-06-05 Paul MackerrasMerge pull request #183 from shawnanastasio/addpcis
2020-06-05 Benjamin Herrenschmidtlitedram: Add support for booting without BRAM
2020-06-03 Paul MackerrasMerge pull request #168 from shenki/flash-arty
2020-06-02 Anton BlanchardMerge pull request #178 from antonblanchard/intercon
2020-05-25 Benjamin Herrenschmidtirq: Simplify xics->core irq input
2020-05-25 Benjamin Herrenschmidtsoc: Rework interconnect
2020-05-25 Benjamin Herrenschmidtsw: Add full memory map to .h and use it for litedram...
2020-05-19 Anton BlanchardMerge pull request #173 from Jbalkind/core-vcs-syntax
2020-05-19 Anton BlanchardMerge pull request #177 from antonblanchard/litedram
2020-05-19 Anton BlanchardMerge branch 'master' into litedram
2020-05-19 Anton BlanchardMerge pull request #176 from antonblanchard/console...
2020-05-19 Anton BlanchardMerge pull request #174 from antonblanchard/yosys-fixes
2020-05-18 Anton BlanchardMerge pull request #169 from paulusmack/mmu
2020-05-16 Benjamin Herrenschmidtsoc/core: Add reset latches
2020-05-16 Benjamin Herrenschmidtlitedram: Update to new LiteX/LiteDRAM version
2020-05-14 Paul Mackerrassoc: Work around compile error with ghdl 0.37-dev
2020-05-14 Paul MackerrasMerge branch 'mmu'
2020-05-14 Anton BlanchardMerge pull request #170 from antonblanchard/litedram
2020-05-09 Benjamin Herrenschmidtlitedram: Add support for Microwatt-initialized controller
2020-05-08 Benjamin Herrenschmidtsyscon: Add syscon registers
2020-05-08 Benjamin Herrenschmidtsoc: Add DRAM address decoding
2020-05-08 Benjamin Herrenschmidtcore: Add alternate reset address
2020-05-06 Paul MackerrasMerge remote-tracking branch 'remotes/origin/master'
2020-05-06 Anton BlanchardMerge pull request #165 from mikey/xics
2020-04-23 Michael NeulingXICS interrupt controller
2020-01-11 Anton BlanchardMerge pull request #133 from antonblanchard/ghdl-synth
2020-01-11 Anton BlanchardRemoved unused core_terminated signal
2019-11-15 Anton BlanchardMerge pull request #118 from antonblanchard/bus-pipeline
2019-10-30 Benjamin Herrenschmidtwb_arbiter: Make arbiter size parametric
2019-10-30 Benjamin Herrenschmidtram: Rework main RAM interface
2019-10-30 Benjamin HerrenschmidtAdd option to not flatten hierarchy
2019-10-30 Benjamin Herrenschmidtintercon: Generate stall signals for non-pipelined...
2019-10-25 Anton BlanchardMerge pull request #115 from antonblanchard/reduce...
2019-10-23 Benjamin HerrenschmidtReduce wishbone address size to 32-bit
2019-10-11 Anton BlanchardMerge pull request #84 from classilla/master
2019-10-11 Anton BlanchardMerge pull request #89 from mikey/gitignore
2019-10-10 Anton BlanchardMerge pull request #86 from antonblanchard/outstanding...
2019-10-10 Anton BlanchardMerge pull request #85 from antonblanchard/leadingzeroe...
2019-10-10 Anton BlanchardMerge pull request #79 from deece/uart_address
2019-10-08 Alastair D'SilvaTighten UART address
2019-09-24 Anton BlanchardMerge branch 'divider' of https://github.com/paulusmack...
2019-09-24 Anton BlanchardMerge pull request #69 from antonblanchard/debug-module
2019-09-20 Benjamin HerrenschmidtAdd core debug module
2019-09-20 Benjamin HerrenschmidtAdd DMI address decoder
2019-09-20 Benjamin HerrenschmidtWishbone debug module
2019-09-20 Benjamin HerrenschmidtAdd a debug (DMI) bus and a JTAG interface to it on...
2019-09-20 Benjamin HerrenschmidtUse a 3 way WB arbiter and cleanup fpga toplevel
2019-09-10 Benjamin HerrenschmidtSwitch soc to use std_ulogic
2019-09-10 Benjamin HerrenschmidtShare soc.vhdl between FPGA and sim