wishbone: fix SRAM; improve tests for Decoder & Arbiter
[nmigen-soc.git] / .coveragerc
1 [run]
2 branch = True
3 include =
4 nmigen_soc/*
5 omit =
6 nmigen_soc/test/*
7 */__init__.py
8
9 [report]
10 exclude_lines =
11 :nocov:
12 partial_branches =
13 :nobr: