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wishbone: fix SRAM; improve tests for Decoder & Arbiter
[nmigen-soc.git]
/
.coveragerc
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[run]
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branch = True
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include =
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nmigen_soc/*
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omit =
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nmigen_soc/test/*
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*/__init__.py
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[report]
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exclude_lines =
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:nocov:
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partial_branches =
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:nobr: