1 # nmigen: UnusedElaboratable=no
5 from nmigen
.hdl
.rec
import Layout
6 from nmigen
.back
.pysim
import *
8 from ..csr
.bus
import *
11 class ElementTestCase(unittest
.TestCase
):
12 def test_layout_1_ro(self
):
13 elem
= Element(1, "r")
14 self
.assertEqual(elem
.width
, 1)
15 self
.assertEqual(elem
.access
, Element
.Access
.R
)
16 self
.assertEqual(elem
.layout
, Layout
.cast([
21 def test_layout_8_rw(self
):
22 elem
= Element(8, access
="rw")
23 self
.assertEqual(elem
.width
, 8)
24 self
.assertEqual(elem
.access
, Element
.Access
.RW
)
25 self
.assertEqual(elem
.layout
, Layout
.cast([
32 def test_layout_10_wo(self
):
33 elem
= Element(10, "w")
34 self
.assertEqual(elem
.width
, 10)
35 self
.assertEqual(elem
.access
, Element
.Access
.W
)
36 self
.assertEqual(elem
.layout
, Layout
.cast([
41 def test_layout_0_rw(self
): # degenerate but legal case
42 elem
= Element(0, access
=Element
.Access
.RW
)
43 self
.assertEqual(elem
.width
, 0)
44 self
.assertEqual(elem
.access
, Element
.Access
.RW
)
45 self
.assertEqual(elem
.layout
, Layout
.cast([
52 def test_width_wrong(self
):
53 with self
.assertRaisesRegex(ValueError,
54 r
"Width must be a non-negative integer, not -1"):
57 def test_access_wrong(self
):
58 with self
.assertRaisesRegex(ValueError,
59 r
"Access mode must be one of \"r
\", \"w
\", "
60 r"or \"rw
\", not 'wo'"):
64 class InterfaceTestCase(unittest.TestCase):
65 def test_layout(self):
66 iface = Interface(addr_width=12, data_width=8)
67 self.assertEqual(iface.addr_width, 12)
68 self.assertEqual(iface.data_width, 8)
69 self.assertEqual(iface.layout, Layout.cast([
77 def test_wrong_addr_width(self):
78 with self.assertRaisesRegex(ValueError,
79 r"Address width must be a positive integer
, not -1"):
80 Interface(addr_width=-1, data_width=8)
82 def test_wrong_data_width(self):
83 with self.assertRaisesRegex(ValueError,
84 r"Data width must be a positive integer
, not -1"):
85 Interface(addr_width=16, data_width=-1)
88 class MultiplexerTestCase(unittest.TestCase):
90 self.dut = Multiplexer(addr_width=16, data_width=8)
92 def test_add_4b(self):
93 self.assertEqual(self.dut.add(Element(4, "rw
")),
96 def test_add_8b(self):
97 self.assertEqual(self.dut.add(Element(8, "rw
")),
100 def test_add_12b(self):
101 self.assertEqual(self.dut.add(Element(12, "rw
")),
104 def test_add_16b(self):
105 self.assertEqual(self.dut.add(Element(16, "rw
")),
108 def test_add_two(self):
109 self.assertEqual(self.dut.add(Element(16, "rw
")),
111 self.assertEqual(self.dut.add(Element(8, "rw
")),
114 def test_add_wrong(self):
115 with self.assertRaisesRegex(TypeError,
116 r"Element must be an instance of csr\
.Element
, not 'foo'"):
119 def test_align_to(self):
120 self.assertEqual(self.dut.add(Element(8, "rw
")),
122 self.assertEqual(self.dut.align_to(2), 4)
123 self.assertEqual(self.dut.add(Element(8, "rw
")),
129 elem_4_r = Element(4, "r
")
130 self.dut.add(elem_4_r)
131 elem_8_w = Element(8, "w
")
132 self.dut.add(elem_8_w)
133 elem_16_rw = Element(16, "rw
")
134 self.dut.add(elem_16_rw)
137 yield elem_4_r.r_data.eq(0xa)
138 yield elem_16_rw.r_data.eq(0x5aa5)
141 yield bus.r_stb.eq(1)
143 yield bus.r_stb.eq(0)
144 self.assertEqual((yield elem_4_r.r_stb), 1)
145 self.assertEqual((yield elem_16_rw.r_stb), 0)
147 self.assertEqual((yield bus.r_data), 0xa)
150 yield bus.r_stb.eq(1)
152 yield bus.r_stb.eq(0)
153 self.assertEqual((yield elem_4_r.r_stb), 0)
154 self.assertEqual((yield elem_16_rw.r_stb), 1)
156 yield bus.addr.eq(3) # pipeline a read
157 self.assertEqual((yield bus.r_data), 0xa5)
159 yield bus.r_stb.eq(1)
161 yield bus.r_stb.eq(0)
162 self.assertEqual((yield elem_4_r.r_stb), 0)
163 self.assertEqual((yield elem_16_rw.r_stb), 0)
165 self.assertEqual((yield bus.r_data), 0x5a)
168 yield bus.w_data.eq(0x3d)
169 yield bus.w_stb.eq(1)
171 yield bus.w_stb.eq(0)
172 yield bus.addr.eq(2) # change address
174 self.assertEqual((yield elem_8_w.w_stb), 1)
175 self.assertEqual((yield elem_8_w.w_data), 0x3d)
176 self.assertEqual((yield elem_16_rw.w_stb), 0)
178 self.assertEqual((yield elem_8_w.w_stb), 0)
181 yield bus.w_data.eq(0x55)
182 yield bus.w_stb.eq(1)
184 self.assertEqual((yield elem_8_w.w_stb), 0)
185 self.assertEqual((yield elem_16_rw.w_stb), 0)
186 yield bus.addr.eq(3) # pipeline a write
187 yield bus.w_data.eq(0xaa)
189 self.assertEqual((yield elem_8_w.w_stb), 0)
190 self.assertEqual((yield elem_16_rw.w_stb), 0)
191 yield bus.w_stb.eq(0)
193 self.assertEqual((yield elem_8_w.w_stb), 0)
194 self.assertEqual((yield elem_16_rw.w_stb), 1)
195 self.assertEqual((yield elem_16_rw.w_data), 0xaa55)
197 with Simulator(self.dut, vcd_file=open("test
.vcd
", "w
")) as sim:
199 sim.add_sync_process(sim_test())
203 class MultiplexerAlignedTestCase(unittest.TestCase):
205 self.dut = Multiplexer(addr_width=16, data_width=8, alignment=2)
207 def test_add_two(self):
208 self.assertEqual(self.dut.add(Element(8, "rw
")),
210 self.assertEqual(self.dut.add(Element(16, "rw
")),
213 def test_over_align_to(self):
214 self.assertEqual(self.dut.add(Element(8, "rw
")),
216 self.assertEqual(self.dut.align_to(3), 8)
217 self.assertEqual(self.dut.add(Element(8, "rw
")),
220 def test_under_align_to(self):
221 self.assertEqual(self.dut.add(Element(8, "rw
")),
223 self.assertEqual(self.dut.align_to(1), 4)
224 self.assertEqual(self.dut.add(Element(8, "rw
")),
230 elem_20_rw = Element(20, "rw
")
231 self.dut.add(elem_20_rw)
234 yield bus.w_stb.eq(1)
236 yield bus.w_data.eq(0x55)
238 self.assertEqual((yield elem_20_rw.w_stb), 0)
240 yield bus.w_data.eq(0xaa)
242 self.assertEqual((yield elem_20_rw.w_stb), 0)
244 yield bus.w_data.eq(0x33)
246 self.assertEqual((yield elem_20_rw.w_stb), 0)
248 yield bus.w_data.eq(0xdd)
250 self.assertEqual((yield elem_20_rw.w_stb), 0)
251 yield bus.w_stb.eq(0)
253 self.assertEqual((yield elem_20_rw.w_stb), 1)
254 self.assertEqual((yield elem_20_rw.w_data), 0x3aa55)
256 with Simulator(self.dut, vcd_file=open("test
.vcd
", "w
")) as sim:
258 sim.add_sync_process(sim_test())
262 class DecoderTestCase(unittest.TestCase):
264 self.dut = Decoder(addr_width=16, data_width=8)
266 def test_align_to(self):
267 self.assertEqual(self.dut.add(Interface(addr_width=10, data_width=8)),
269 self.assertEqual(self.dut.align_to(12), 0x1000)
270 self.assertEqual(self.dut.add(Interface(addr_width=10, data_width=8)),
273 def test_add_wrong_sub_bus(self):
274 with self.assertRaisesRegex(TypeError,
275 r"Subordinate bus must be an instance of
"
276 r"csr\
.Interface
, not 1"):
279 def test_add_wrong_data_width(self):
280 mux = Multiplexer(addr_width=10, data_width=16)
281 Fragment.get(mux, platform=None) # silence UnusedElaboratable
283 with self.assertRaisesRegex(ValueError,
284 r"Subordinate bus has data width
16, which
is not the same
as "
285 r"decoder data width
8"):
286 self.dut.add(mux.bus)
289 mux_1 = Multiplexer(addr_width=10, data_width=8)
290 self.dut.add(mux_1.bus)
291 elem_1 = Element(8, "rw
")
294 mux_2 = Multiplexer(addr_width=10, data_width=8)
295 self.dut.add(mux_2.bus)
296 elem_2 = Element(8, "rw
")
297 mux_2.add(elem_2, addr=2)
299 elem_1_addr, _, _ = self.dut.bus.memory_map.find_resource(elem_1)
300 elem_2_addr, _, _ = self.dut.bus.memory_map.find_resource(elem_2)
301 self.assertEqual(elem_1_addr, 0x0000)
302 self.assertEqual(elem_2_addr, 0x0402)
307 yield bus.addr.eq(elem_1_addr)
308 yield bus.w_stb.eq(1)
309 yield bus.w_data.eq(0x55)
311 yield bus.w_stb.eq(0)
313 self.assertEqual((yield elem_1.w_data), 0x55)
315 yield bus.addr.eq(elem_2_addr)
316 yield bus.w_stb.eq(1)
317 yield bus.w_data.eq(0xaa)
319 yield bus.w_stb.eq(0)
321 self.assertEqual((yield elem_2.w_data), 0xaa)
323 yield elem_1.r_data.eq(0x55)
324 yield elem_2.r_data.eq(0xaa)
326 yield bus.addr.eq(elem_1_addr)
327 yield bus.r_stb.eq(1)
329 yield bus.addr.eq(elem_2_addr)
331 self.assertEqual((yield bus.r_data), 0x55)
333 self.assertEqual((yield bus.r_data), 0xaa)
336 m.submodules += self.dut, mux_1, mux_2
337 with Simulator(m, vcd_file=open("test
.vcd
", "w
")) as sim:
339 sim.add_sync_process(sim_test())