nmigen_soc/test/test_csr_bus.py

   1 import unittest
   2 from nmigen import *
   3 from nmigen.hdl.rec import Layout
   4 from nmigen.back.pysim import *
   5
   6 from ..csr.bus import *
   7
   8
   9 class ElementTestCase(unittest.TestCase):
  10     def test_layout_1_ro(self):
  11         elem = Element(1, "r")
  12         self.assertEqual(elem.width, 1)
  13         self.assertEqual(elem.access, "r")
  14         self.assertEqual(elem.layout, Layout.cast([
  15             ("r_data", 1),
  16             ("r_stb", 1),
  17         ]))
  18
  19     def test_layout_8_rw(self):
  20         elem = Element(8, access="rw")
  21         self.assertEqual(elem.width, 8)
  22         self.assertEqual(elem.access, "rw")
  23         self.assertEqual(elem.layout, Layout.cast([
  24             ("r_data", 8),
  25             ("r_stb", 1),
  26             ("w_data", 8),
  27             ("w_stb", 1),
  28         ]))
  29
  30     def test_layout_10_wo(self):
  31         elem = Element(10, "w")
  32         self.assertEqual(elem.width, 10)
  33         self.assertEqual(elem.access, "w")
  34         self.assertEqual(elem.layout, Layout.cast([
  35             ("w_data", 10),
  36             ("w_stb", 1),
  37         ]))
  38
  39     def test_layout_0_rw(self): # degenerate but legal case
  40         elem = Element(0, access="rw")
  41         self.assertEqual(elem.width, 0)
  42         self.assertEqual(elem.access, "rw")
  43         self.assertEqual(elem.layout, Layout.cast([
  44             ("r_data", 0),
  45             ("r_stb", 1),
  46             ("w_data", 0),
  47             ("w_stb", 1),
  48         ]))
  49
  50     def test_width_wrong(self):
  51         with self.assertRaisesRegex(ValueError,
  52                 r"Width must be a non-negative integer, not -1"):
  53             Element(-1, "rw")
  54
  55     def test_access_wrong(self):
  56         with self.assertRaisesRegex(ValueError,
  57                 r"Access mode must be one of \"r\", \"w\", or \"rw\", not 'wo'"):
  58             Element(1, "wo")
  59
  60
  61 class InterfaceTestCase(unittest.TestCase):
  62     def test_layout(self):
  63         iface = Interface(addr_width=12, data_width=8)
  64         self.assertEqual(iface.addr_width, 12)
  65         self.assertEqual(iface.data_width, 8)
  66         self.assertEqual(iface.layout, Layout.cast([
  67             ("addr",    12),
  68             ("r_data",  8),
  69             ("r_stb",   1),
  70             ("w_data",  8),
  71             ("w_stb",   1),
  72         ]))
  73
  74     def test_addr_width_wrong(self):
  75         with self.assertRaisesRegex(ValueError,
  76                 r"Address width must be a positive integer, not -1"):
  77             Interface(addr_width=-1, data_width=8)
  78
  79     def test_data_width_wrong(self):
  80         with self.assertRaisesRegex(ValueError,
  81                 r"Data width must be a positive integer, not -1"):
  82             Interface(addr_width=16, data_width=-1)
  83
  84
  85 class DecoderTestCase(unittest.TestCase):
  86     def setUp(self):
  87         self.dut = Decoder(addr_width=16, data_width=8)
  88
  89     def test_alignment_wrong(self):
  90         with self.assertRaisesRegex(ValueError,
  91                 r"Alignment must be a non-negative integer, not -1"):
  92             Decoder(addr_width=16, data_width=8, alignment=-1)
  93
  94     def test_attrs(self):
  95         self.assertEqual(self.dut.alignment, 0)
  96
  97     def test_add_4b(self):
  98         self.assertEqual(self.dut.add(Element(4, "rw")),
  99                          (0, 1))
 100
 101     def test_add_8b(self):
 102         self.assertEqual(self.dut.add(Element(8, "rw")),
 103                          (0, 1))
 104
 105     def test_add_12b(self):
 106         self.assertEqual(self.dut.add(Element(12, "rw")),
 107                          (0, 2))
 108
 109     def test_add_16b(self):
 110         self.assertEqual(self.dut.add(Element(16, "rw")),
 111                          (0, 2))
 112
 113     def test_add_two(self):
 114         self.assertEqual(self.dut.add(Element(16, "rw")),
 115                          (0, 2))
 116         self.assertEqual(self.dut.add(Element(8, "rw")),
 117                          (2, 1))
 118
 119     def test_add_wrong(self):
 120         with self.assertRaisesRegex(ValueError,
 121                 r"Width must be a non-negative integer, not -1"):
 122             Element(-1, "rw")
 123
 124     def test_align_to(self):
 125         self.assertEqual(self.dut.add(Element(8, "rw")),
 126                          (0, 1))
 127         self.assertEqual(self.dut.align_to(2), 4)
 128         self.assertEqual(self.dut.add(Element(8, "rw")),
 129                          (4, 1))
 130
 131     def test_sim(self):
 132         bus = self.dut.bus
 133
 134         elem_4_r = Element(4, "r")
 135         self.dut.add(elem_4_r)
 136         elem_8_w = Element(8, "w")
 137         self.dut.add(elem_8_w)
 138         elem_16_rw = Element(16, "rw")
 139         self.dut.add(elem_16_rw)
 140
 141         def sim_test():
 142             yield elem_4_r.r_data.eq(0xa)
 143             yield elem_16_rw.r_data.eq(0x5aa5)
 144
 145             yield bus.addr.eq(0)
 146             yield bus.r_stb.eq(1)
 147             yield
 148             yield bus.r_stb.eq(0)
 149             self.assertEqual((yield elem_4_r.r_stb), 1)
 150             self.assertEqual((yield elem_16_rw.r_stb), 0)
 151             yield
 152             self.assertEqual((yield bus.r_data), 0xa)
 153
 154             yield bus.addr.eq(2)
 155             yield bus.r_stb.eq(1)
 156             yield
 157             yield bus.r_stb.eq(0)
 158             self.assertEqual((yield elem_4_r.r_stb), 0)
 159             self.assertEqual((yield elem_16_rw.r_stb), 1)
 160             yield
 161             yield bus.addr.eq(3) # pipeline a read
 162             self.assertEqual((yield bus.r_data), 0xa5)
 163
 164             yield bus.r_stb.eq(1)
 165             yield
 166             yield bus.r_stb.eq(0)
 167             self.assertEqual((yield elem_4_r.r_stb), 0)
 168             self.assertEqual((yield elem_16_rw.r_stb), 0)
 169             yield
 170             self.assertEqual((yield bus.r_data), 0x5a)
 171
 172             yield bus.addr.eq(1)
 173             yield bus.w_data.eq(0x3d)
 174             yield bus.w_stb.eq(1)
 175             yield
 176             yield bus.w_stb.eq(0)
 177             yield
 178             self.assertEqual((yield elem_8_w.w_stb), 1)
 179             self.assertEqual((yield elem_8_w.w_data), 0x3d)
 180             self.assertEqual((yield elem_16_rw.w_stb), 0)
 181
 182             yield bus.addr.eq(2)
 183             yield bus.w_data.eq(0x55)
 184             yield bus.w_stb.eq(1)
 185             yield
 186             self.assertEqual((yield elem_8_w.w_stb), 0)
 187             self.assertEqual((yield elem_16_rw.w_stb), 0)
 188             yield bus.addr.eq(3) # pipeline a write
 189             yield bus.w_data.eq(0xaa)
 190             yield
 191             self.assertEqual((yield elem_8_w.w_stb), 0)
 192             self.assertEqual((yield elem_16_rw.w_stb), 0)
 193             yield bus.w_stb.eq(0)
 194             yield
 195             self.assertEqual((yield elem_8_w.w_stb), 0)
 196             self.assertEqual((yield elem_16_rw.w_stb), 1)
 197             self.assertEqual((yield elem_16_rw.w_data), 0xaa55)
 198
 199         with Simulator(self.dut, vcd_file=open("test.vcd", "w")) as sim:
 200             sim.add_clock(1e-6)
 201             sim.add_sync_process(sim_test())
 202             sim.run()
 203
 204
 205 class DecoderAlignedTestCase(unittest.TestCase):
 206     def setUp(self):
 207         self.dut = Decoder(addr_width=16, data_width=8, alignment=2)
 208
 209     def test_attrs(self):
 210         self.assertEqual(self.dut.alignment, 2)
 211
 212     def test_add_two(self):
 213         self.assertEqual(self.dut.add(Element(8, "rw")),
 214                          (0, 4))
 215         self.assertEqual(self.dut.add(Element(16, "rw")),
 216                          (4, 4))
 217
 218     def test_over_align_to(self):
 219         self.assertEqual(self.dut.add(Element(8, "rw")),
 220                          (0, 4))
 221         self.assertEqual(self.dut.align_to(3), 8)
 222         self.assertEqual(self.dut.add(Element(8, "rw")),
 223                          (8, 4))
 224
 225     def test_under_align_to(self):
 226         self.assertEqual(self.dut.add(Element(8, "rw")),
 227                          (0, 4))
 228         self.assertEqual(self.dut.align_to(1), 4)
 229         self.assertEqual(self.dut.add(Element(8, "rw")),
 230                          (4, 4))
 231
 232     def test_sim(self):
 233         bus = self.dut.bus
 234
 235         elem_20_rw = Element(20, "rw")
 236         self.dut.add(elem_20_rw)
 237
 238         def sim_test():
 239             yield bus.w_stb.eq(1)
 240             yield bus.addr.eq(0)
 241             yield bus.w_data.eq(0x55)
 242             yield
 243             self.assertEqual((yield elem_20_rw.w_stb), 0)
 244             yield bus.addr.eq(1)
 245             yield bus.w_data.eq(0xaa)
 246             yield
 247             self.assertEqual((yield elem_20_rw.w_stb), 0)
 248             yield bus.addr.eq(2)
 249             yield bus.w_data.eq(0x33)
 250             yield
 251             self.assertEqual((yield elem_20_rw.w_stb), 0)
 252             yield bus.addr.eq(3)
 253             yield bus.w_data.eq(0xdd)
 254             yield
 255             self.assertEqual((yield elem_20_rw.w_stb), 0)
 256             yield bus.w_stb.eq(0)
 257             yield
 258             self.assertEqual((yield elem_20_rw.w_stb), 1)
 259             self.assertEqual((yield elem_20_rw.w_data), 0x3aa55)
 260
 261         with Simulator(self.dut, vcd_file=open("test.vcd", "w")) as sim:
 262             sim.add_clock(1e-6)
 263             sim.add_sync_process(sim_test())
 264             sim.run()