37ce285b686dbd0915903c98d7a5d247197548b7
2 from nmigen
import Record
, Elaboratable
, Module
, Signal
, Cat
, Repl
3 from nmigen
.hdl
.rec
import Direction
4 from nmigen
.utils
import log2_int
6 from ..memory
import MemoryMap
7 from ..scheduler
import *
10 __all__
= ["CycleType", "BurstTypeExt", "Interface", "Decoder",
11 "Arbiter", "InterconnectShared"]
14 class CycleType(Enum
):
15 """Wishbone Registered Feedback cycle type."""
22 class BurstTypeExt(Enum
):
23 """Wishbone Registered Feedback burst type extension."""
30 class Interface(Record
):
31 """Wishbone interface.
33 See the `Wishbone specification
34 <https://opencores.org/howto/wishbone>`_ for description of the
35 Wishbone signals. The ``RST_I`` and ``CLK_I`` signals are provided
36 as a part of the clock domain that drives the interface.
38 Note that the data width of the underlying memory map of the interface
39 is equal to port granularity, not port size. If port granularity is
40 less than port size, then the address width of the underlying memory
41 map is extended to reflect that.
46 Width of the address signal.
48 Width of the data signals ("port size" in Wishbone terminology).
50 granularity : int or None
51 Granularity of select signals ("port granularity" in Wishbone
52 terminology). One of 8, 16, 32, 64. Optional and defaults to
53 None, meaning it is equal to the address width.
55 Selects the optional signals that will be a part of this interface.
57 Resource and window alignment. Optional. See :class:`MemoryMap`.
59 Name of the underlying record.
63 The correspondence between the nMigen-SoC signals and the Wishbone
64 signals changes depending on whether the interface acts as an
65 initiator or a target.
67 adr : Signal(addr_width)
68 Corresponds to Wishbone signal ``ADR_O`` (initiator) or ``ADR_I``
70 dat_w : Signal(data_width)
71 Corresponds to Wishbone signal ``DAT_O`` (initiator) or ``DAT_I``
73 dat_r : Signal(data_width)
74 Corresponds to Wishbone signal ``DAT_I`` (initiator) or ``DAT_O``
76 sel : Signal(data_width // granularity)
77 Corresponds to Wishbone signal ``SEL_O`` (initiator) or ``SEL_I``
80 Corresponds to Wishbone signal ``CYC_O`` (initiator) or ``CYC_I``
83 Corresponds to Wishbone signal ``STB_O`` (initiator) or ``STB_I``
86 Corresponds to Wishbone signal ``WE_O`` (initiator) or ``WE_I``
89 Corresponds to Wishbone signal ``ACK_I`` (initiator) or ``ACK_O``
92 Optional. Corresponds to Wishbone signal ``ERR_I`` (initiator)
93 or ``ERR_O`` (target).
95 Optional. Corresponds to Wishbone signal ``RTY_I`` (initiator)
96 or ``RTY_O`` (target).
98 Optional. Corresponds to Wishbone signal ``STALL_I`` (initiator)
99 or ``STALL_O`` (target).
101 Optional. Corresponds to Wishbone signal ``LOCK_O`` (initiator)
102 or ``LOCK_I`` (target).
104 Optional. Corresponds to Wishbone signal ``CTI_O`` (initiator)
105 or ``CTI_I`` (target).
107 Optional. Corresponds to Wishbone signal ``BTE_O`` (initiator)
108 or ``BTE_I`` (target).
111 def __init__(self
, *, addr_width
, data_width
, granularity
=None,
113 alignment
=0, name
=None):
115 features
= frozenset()
116 if not isinstance(addr_width
, int) or addr_width
< 0:
117 raise ValueError("Address width must be a non-negative integer, "
118 "not {!r}" .format(addr_width
))
119 if data_width
not in (8, 16, 32, 64):
120 raise ValueError("Data width must be one of 8, 16, 32, 64, not {!r}"
122 if granularity
is None:
123 granularity
= data_width
124 elif granularity
not in (8, 16, 32, 64):
125 raise ValueError("Granularity must be one of 8, 16, 32, 64, "
126 "not {!r}" .format(granularity
))
127 if granularity
> data_width
:
128 raise ValueError("Granularity {} may not be greater than data "
129 "width {}" .format(granularity
, data_width
))
130 self
.addr_width
= addr_width
131 self
.data_width
= data_width
132 self
.granularity
= granularity
133 granularity_bits
= log2_int(data_width
// granularity
)
134 self
._alignment
= alignment
135 self
.memory_map
= MemoryMap(addr_width
=max(1, addr_width
+
137 data_width
=data_width
>> granularity_bits
,
140 self
._features
= set(features
)
141 unknown
= self
._features
- \
142 {"rty", "err", "stall", "lock", "cti", "bte"}
144 raise ValueError("Optional signal(s) {} are not supported"
145 .format(", ".join(map(repr, unknown
))))
147 ("adr", addr_width
, Direction
.FANOUT
),
148 ("dat_w", data_width
, Direction
.FANOUT
),
149 ("dat_r", data_width
, Direction
.FANIN
),
150 ("sel", data_width
// granularity
, Direction
.FANOUT
),
151 ("cyc", 1, Direction
.FANOUT
),
152 ("stb", 1, Direction
.FANOUT
),
153 ("we", 1, Direction
.FANOUT
),
154 ("ack", 1, Direction
.FANIN
),
156 if "err" in features
:
157 layout
+= [("err", 1, Direction
.FANIN
)]
158 if "rty" in features
:
159 layout
+= [("rty", 1, Direction
.FANIN
)]
160 if "stall" in features
:
161 layout
+= [("stall", 1, Direction
.FANIN
)]
162 if "lock" in features
:
163 layout
+= [("lock", 1, Direction
.FANOUT
)]
164 if "cti" in features
:
165 layout
+= [("cti", CycleType
, Direction
.FANOUT
)]
166 if "bte" in features
:
167 layout
+= [("bte", BurstTypeExt
, Direction
.FANOUT
)]
168 super().__init
__(layout
, name
=name
, src_loc_at
=1)
171 def from_pure_record(cls
, record
):
172 """Instantiate a :class:`wishbone.Interface`
173 from a simple :class:`Record`
175 if not isinstance(record
, Record
):
176 raise TypeError("{!r} is not a Record"
178 addr_width
= len(record
.adr
)
179 if len(record
.dat_w
) != len(record
.dat_r
):
180 raise AttributeError("Record {!r} has {}-bit long \"dat_w\" "
181 "but {}-bit long \"dat_r\""
182 .format(record
, len(record
.dat_w
),
184 data_width
= len(record
.dat_w
)
185 if data_width
% len(record
.sel
) != 0:
186 raise AttributeError("Record {!r} has invalid granularity "
188 "its data width is {}-bit long but "
189 "its \"sel\" is {}-bit long"
190 .format(record
, data_width
, len(record
.sel
)))
191 granularity
= data_width
// len(record
.sel
)
193 for signal_name
in ["rty", "err", "stall", "lock", "cti", "bte"]:
194 if hasattr(record
, signal_name
):
195 features
.append(signal_name
)
196 return cls(addr_width
=addr_width
,
197 data_width
=data_width
,
198 granularity
=granularity
,
201 name
=record
.name
+ "_intf")
204 class Decoder(Elaboratable
):
205 """Wishbone bus decoder.
207 An address decoder for subordinate Wishbone buses.
212 Address width. See :class:`Interface`.
214 Data width. See :class:`Interface`.
215 granularity : int or None
216 Granularity. Optional. See :class:`Interface`
218 Optional signal set. See :class:`Interface`.
220 Window alignment. Optional. See :class:`Interface`.
224 bus : :class:`Interface`
225 Bus providing access to subordinate buses.
228 def __init__(self
, *, addr_width
, data_width
, granularity
=None,
232 features
= frozenset()
233 self
.bus
= Interface(addr_width
=addr_width
, data_width
=data_width
,
234 granularity
=granularity
, features
=features
,
236 self
._map
= self
.bus
.memory_map
239 def align_to(self
, alignment
):
240 """Align the implicit address of the next window.
242 See :meth:`MemoryMap.align_to` for details.
244 return self
._map
.align_to(alignment
)
246 def add(self
, sub_bus
, *, addr
=None, sparse
=False):
247 """Add a window to a subordinate bus.
249 The decoder can perform either sparse or dense address
250 translation. If dense address translation is used (the default),
251 the subordinate bus must have the same data width as the decoder;
252 the window will be contiguous. If sparse address translation is
253 used, the subordinate bus may have data width less than the data
254 width of the decoder; the window may be discontiguous. In either
255 case, the granularity of the subordinate bus must be equal to
256 or less than the granularity of the decoder.
258 See :meth:`MemoryMap.add_resource` for details.
260 if not isinstance(sub_bus
, Interface
):
261 raise TypeError("Subordinate bus must be an instance of "
262 "wishbone.Interface, not {!r}".format(sub_bus
))
263 if sub_bus
.granularity
> self
.bus
.granularity
:
264 raise ValueError("Subordinate bus has granularity {}, "
265 "which is greater than the "
266 "decoder granularity {}"
267 .format(sub_bus
.granularity
, self
.bus
.granularity
))
269 if sub_bus
.data_width
!= self
.bus
.data_width
:
270 raise ValueError("Subordinate bus has data width {}, "
271 "which is not the same as "
272 "decoder data width {} (required "
273 "for dense address translation)"
274 .format(sub_bus
.data_width
,
275 self
.bus
.data_width
))
277 if sub_bus
.granularity
!= sub_bus
.data_width
:
278 raise ValueError("Subordinate bus has data width {}, "
279 "which is not the same as "
280 "subordinate bus granularity {} "
281 "(required for sparse address "
283 .format(sub_bus
.data_width
,
284 sub_bus
.granularity
))
285 for opt_output
in {"err", "rty", "stall"}:
286 if hasattr(sub_bus
, opt_output
) and not hasattr(
287 self
.bus
, opt_output
):
288 raise ValueError("Subordinate bus has optional output {!r}, "
290 "does not have a corresponding input"
293 self
._subs
[sub_bus
.memory_map
] = sub_bus
294 return self
._map
.add_window(
295 sub_bus
.memory_map
, addr
=addr
, sparse
=sparse
)
297 def elaborate(self
, platform
):
305 with m
.Switch(self
.bus
.adr
):
306 for sub_map
, (sub_pat
, sub_ratio
) in self
._map
.window_patterns():
307 sub_bus
= self
._subs
[sub_map
]
310 sub_bus
.adr
.eq(self
.bus
.adr
<< log2_int(sub_ratio
)),
311 sub_bus
.dat_w
.eq(self
.bus
.dat_w
),
312 sub_bus
.sel
.eq(Cat(Repl(sel
, sub_ratio
)
313 for sel
in self
.bus
.sel
)),
314 sub_bus
.we
.eq(self
.bus
.we
),
315 sub_bus
.stb
.eq(self
.bus
.stb
),
317 if hasattr(sub_bus
, "lock"):
318 m
.d
.comb
+= sub_bus
.lock
.eq(getattr(self
.bus
, "lock", 0))
319 if hasattr(sub_bus
, "cti"):
320 m
.d
.comb
+= sub_bus
.cti
.eq(getattr(self
.bus
,
323 if hasattr(sub_bus
, "bte"):
324 m
.d
.comb
+= sub_bus
.bte
.eq(getattr(self
.bus
,
326 BurstTypeExt
.LINEAR
))
328 with m
.Case(sub_pat
[:-log2_int(self
.bus
.data_width
//
329 self
.bus
.granularity
)]):
331 sub_bus
.cyc
.eq(self
.bus
.cyc
),
332 self
.bus
.dat_r
.eq(sub_bus
.dat_r
),
335 ack_fanin |
= sub_bus
.ack
336 if hasattr(sub_bus
, "err"):
337 err_fanin |
= sub_bus
.err
338 if hasattr(sub_bus
, "rty"):
339 rty_fanin |
= sub_bus
.rty
340 if hasattr(sub_bus
, "stall"):
341 stall_fanin |
= sub_bus
.stall
343 m
.d
.comb
+= self
.bus
.ack
.eq(ack_fanin
)
344 if hasattr(self
.bus
, "err"):
345 m
.d
.comb
+= self
.bus
.err
.eq(err_fanin
)
346 if hasattr(self
.bus
, "rty"):
347 m
.d
.comb
+= self
.bus
.rty
.eq(rty_fanin
)
348 if hasattr(self
.bus
, "stall"):
349 m
.d
.comb
+= self
.bus
.stall
.eq(stall_fanin
)
354 class Arbiter(Elaboratable
):
355 """Wishbone bus arbiter.
357 An arbiter for initiators (masters) to access a shared Wishbone bus.
362 Address width of the shared bus. See :class:`Interface`.
364 Data width of the shared bus. See :class:`Interface`.
365 granularity : int or None
366 Granularity of the shared bus. Optional. See :class:`Interface`.
368 Optional signal set for the shared bus. See :class:`Interface`.
370 Method for bus arbitration. Optional and defaults to "rr"
371 (Round Robin, see :class:`scheduler.RoundRobin`).
375 bus : :class:`Interface`
376 Shared bus to which the selected initiator gains access.
379 def __init__(self
, *, addr_width
, data_width
, granularity
=None,
383 features
= frozenset()
384 self
.bus
= Interface(addr_width
=addr_width
, data_width
=data_width
,
385 granularity
=granularity
, features
=features
)
387 if scheduler
not in ["rr"]:
388 raise ValueError("Scheduling mode must be \"rr\", not {!r}"
390 self
._scheduler
= scheduler
392 def add(self
, itor_bus
):
393 """Add an initiator bus to the arbiter.
395 The initiator bus must have the same address width and data
396 width as the arbiter. The granularity of the initiator bus must
397 be greater than or equal to the granularity of the arbiter.
399 if not isinstance(itor_bus
, Interface
):
400 raise TypeError("Initiator bus must be an instance of "
401 "wishbone.Interface, not {!r}".format(itor_bus
))
402 if itor_bus
.addr_width
!= self
.bus
.addr_width
:
403 raise ValueError("Initiator bus has address width {}, "
404 "which is not the same as "
405 "arbiter address width {}"
406 .format(itor_bus
.addr_width
, self
.bus
.addr_width
))
407 if itor_bus
.granularity
< self
.bus
.granularity
:
408 raise ValueError("Initiator bus has granularity {}, "
409 "which is lesser than the "
410 "arbiter granularity {}"
411 .format(itor_bus
.granularity
, self
.bus
.granularity
))
412 if itor_bus
.data_width
!= self
.bus
.data_width
:
413 raise ValueError("Initiator bus has data width {}, "
414 "which is not the same as "
415 "arbiter data width {}"
416 .format(itor_bus
.data_width
, self
.bus
.data_width
))
417 for opt_output
in {"lock", "cti", "bte"}:
418 if hasattr(itor_bus
, opt_output
) and not hasattr(
419 self
.bus
, opt_output
):
420 raise ValueError("Initiator bus has optional output {!r}, "
422 "does not have a corresponding input"
425 self
._itors
.append(itor_bus
)
427 def elaborate(self
, platform
):
430 if self
._scheduler
== "rr":
431 m
.submodules
.scheduler
= scheduler
= RoundRobin(len(self
._itors
))
432 grant
= Signal(range(len(self
._itors
)))
434 # CYC should not be indefinitely asserted. (See RECOMMENDATION 3.05,
436 bus_busy
= self
.bus
.cyc
437 if hasattr(self
.bus
, "lock"):
438 # If LOCK is not asserted, we also wait for STB to be
439 # deasserted before granting bus ownership to the next
440 # initiator. If we didn't, the next bus owner could receive
441 # an ACK (or ERR, RTY) from the previous transaction when
442 # targeting the same peripheral.
443 bus_busy
&= self
.bus
.lock | self
.bus
.stb
446 scheduler
.stb
.eq(~bus_busy
),
447 grant
.eq(scheduler
.grant
),
448 scheduler
.request
.eq(Cat(itor_bus
.cyc
for itor_bus
in self
._itors
))
451 with m
.Switch(grant
):
452 for i
, itor_bus
in enumerate(self
._itors
):
453 m
.d
.comb
+= itor_bus
.dat_r
.eq(self
.bus
.dat_r
)
454 if hasattr(itor_bus
, "stall"):
455 itor_bus_stall
= Signal(reset
=1)
456 m
.d
.comb
+= itor_bus
.stall
.eq(itor_bus_stall
)
459 ratio
= itor_bus
.granularity
// self
.bus
.granularity
461 self
.bus
.adr
.eq(itor_bus
.adr
),
462 self
.bus
.dat_w
.eq(itor_bus
.dat_w
),
463 self
.bus
.sel
.eq(Cat(Repl(sel
, ratio
)
464 for sel
in itor_bus
.sel
)),
465 self
.bus
.we
.eq(itor_bus
.we
),
466 self
.bus
.stb
.eq(itor_bus
.stb
),
468 m
.d
.comb
+= self
.bus
.cyc
.eq(itor_bus
.cyc
)
469 if hasattr(self
.bus
, "lock"):
470 m
.d
.comb
+= self
.bus
.lock
.eq(
471 getattr(itor_bus
, "lock", 1))
472 if hasattr(self
.bus
, "cti"):
473 m
.d
.comb
+= self
.bus
.cti
.eq(
474 getattr(itor_bus
, "cti", CycleType
.CLASSIC
))
475 if hasattr(self
.bus
, "bte"):
476 m
.d
.comb
+= self
.bus
.bte
.eq(
477 getattr(itor_bus
, "bte", BurstTypeExt
.LINEAR
))
479 m
.d
.comb
+= itor_bus
.ack
.eq(self
.bus
.ack
)
480 if hasattr(itor_bus
, "err"):
481 m
.d
.comb
+= itor_bus
.err
.eq(
482 getattr(self
.bus
, "err", 0))
483 if hasattr(itor_bus
, "rty"):
484 m
.d
.comb
+= itor_bus
.rty
.eq(
485 getattr(self
.bus
, "rty", 0))
486 if hasattr(itor_bus
, "stall"):
487 m
.d
.comb
+= itor_bus_stall
.eq(
488 getattr(self
.bus
, "stall", ~self
.bus
.ack
))
493 class InterconnectShared(Elaboratable
):
494 """Wishbone bus interconnect module.
496 This is initialised using the following components:
497 (1) A shared Wishbone bus connecting multiple initiators (MASTERs) with
498 multiple targeted SLAVEs;
499 (2) A list of initiator Wishbone busses; and
500 (3) A list of SLAVE Wishbone busses targeted by the MASTERs.
502 This instantiates the following components:
503 (1) An arbiter (:class:`Arbiter`) controlling access of
504 multiple MASTERs to the shared bus; and
505 (2) A decoder (:class:`Decoder`) specifying which targeted SLAVE is
506 to be accessed using address translation on the shared bus.
508 See Section 8.2.3 of Wishbone B4 for implemenation specifications.
513 Address width of the shared bus. See :class:`Interface`.
515 Data width of the shared bus. See :class:`Interface`.
516 itors : list of (:class:`Interface` OR :class:`Record`)
517 List of MASTERs on the arbiter to request access to the shared bus.
518 If the item is a :class:`Record`, its fields must be named using the
519 convention of :class:`Interface`.
520 targets : list of (:class:`Interface` OR tuple of (:class:`Interface`, int))
521 List of SLAVEs on the decoder whose accesses are to be targeted
522 by the shared bus. If the item is a tuple of (intf, addr), the
523 :class:`Interface`-type intf is added at the (address width +
524 granularity bits)-wide address of the int-type addr.
525 granularity : int or None
526 Granularity of the shared bus. Optional. See :class:`Interface`.
528 Optional signal set for the shared bus. See :class:`Interface`.
530 Method for bus arbitration for the arbiter. Optional and defaults
531 to "rr" (Round Robin, see :class:`scheduler.RoundRobin`).
533 Window alignment for the decoder. Optional. See :class:`Interface`.
537 arbiter : :class:`Arbiter`
538 The arbiter that connects the list of MASTERs to a shared bus.
539 decoder : :class:`Decoder`
540 The decoder that connects the shared bus to the list of SLAVEs.
543 def __init__(self
, *, addr_width
, data_width
, itors
, targets
, **kwargs
):
544 self
.addr_width
= addr_width
545 self
.data_width
= data_width
550 self
._itors
_convert
_stmts
= []
551 for itor_bus
in itors
:
552 if isinstance(itor_bus
, Interface
):
553 self
._itors
.append(itor_bus
)
554 elif isinstance(itor_bus
, Record
):
555 master_interface
= Interface
.from_pure_record(itor_bus
)
556 self
._itors
_convert
_stmts
.append(
557 itor_bus
.connect(master_interface
)
559 self
._itors
.append(master_interface
)
561 raise TypeError("Master {!r} must be a Wishbone interface"
564 for target_bus
in targets
:
565 self
._targets
.append(target_bus
)
567 arbiter_kwargs
= dict()
568 for name
in ["granularity", "features", "scheduler"]:
570 arbiter_kwargs
[name
] = kwargs
[name
]
571 self
.arbiter
= Arbiter(
572 addr_width
=self
.addr_width
, data_width
=self
.data_width
,
575 self
.arbiter
.bus
.name
= "arbiter_shared"
576 for itor_bus
in self
._itors
:
577 self
.arbiter
.add(itor_bus
)
579 decoder_kwargs
= dict()
580 for name
in ["granularity", "features", "alignment"]:
582 decoder_kwargs
[name
] = kwargs
[name
]
583 self
.decoder
= Decoder(addr_width
=self
.addr_width
,
584 data_width
=self
.data_width
,
586 self
.decoder
.bus
.name
= "decoder_shared"
587 for item
in self
._targets
:
588 if isinstance(item
, Interface
):
589 self
.decoder
.add(item
)
590 elif isinstance(item
, tuple) and len(item
) == 2:
591 self
.decoder
.add(item
[0], addr
=item
[1])
593 raise TypeError("Target must be a Wishbone interface, "
594 "or a (Wishbone interface, "
595 "start address) tuple, not {!r}"
598 def elaborate(self
, platform
):
601 m
.submodules
.arbiter
= self
.arbiter
602 m
.submodules
.decoder
= self
.decoder
605 self
._itors
_convert
_stmts
+
606 self
.arbiter
.bus
.connect(self
.decoder
.bus
)