fix nmigen imports

[nmigen-soc.git] / nmigen_soc / csr / bus.py

diff --git a/nmigen_soc/csr/bus.py b/nmigen_soc/csr/bus.py
index b865a01835669242c17be1dba094621cc69718fb..4c6c6ac98618febe8ea58191b2d4276e2662dfe1 100644 (file)
--- a/nmigen_soc/csr/bus.py
+++ b/nmigen_soc/csr/bus.py
@@ -1,5 +1,5 @@
 import enum
-from nmigen import *
+from nmigen import Record, Elaboratable, Module, Signal, Mux
 from nmigen.utils import log2_int
 
 from ..memory import MemoryMap