resolve internal (nmigen_soc) imports

[nmigen-soc.git] / nmigen_soc / csr / bus.py

diff --git a/nmigen_soc/csr/bus.py b/nmigen_soc/csr/bus.py
index 4c6c6ac98618febe8ea58191b2d4276e2662dfe1..91e9930e84f4c8b6e9980b7ff4f138ead4fa43c3 100644 (file)
--- a/nmigen_soc/csr/bus.py
+++ b/nmigen_soc/csr/bus.py
@@ -2,7 +2,7 @@ import enum
 from nmigen import Record, Elaboratable, Module, Signal, Mux
 from nmigen.utils import log2_int
 
-from ..memory import MemoryMap
+from nmigen_soc.memory import MemoryMap
 
 
 __all__ = ["Element", "Interface", "Decoder", "Multiplexer"]