resolve internal (nmigen_soc) imports

[nmigen-soc.git] / nmigen_soc / test / test_csr_bus.py

diff --git a/nmigen_soc/test/test_csr_bus.py b/nmigen_soc/test/test_csr_bus.py
index e53331839a316ec7648fa15e6406a2fded36caca..36d46e30e67711016f3a7826bd7e26ca3e865115 100644 (file)
--- a/nmigen_soc/test/test_csr_bus.py
+++ b/nmigen_soc/test/test_csr_bus.py
@@ -5,7 +5,7 @@ from nmigen import Record, Module
 from nmigen.hdl.rec import Layout
 from nmigen.back.pysim import Simulator, Fragment
 
-from ..csr.bus import *
+from nmigen_soc.csr.bus import Element, Interface, Decoder, Multiplexer
 
 
 class ElementTestCase(unittest.TestCase):