more whitespace cleanup

[nmigen-soc.git] / nmigen_soc / test / test_csr_bus.py

diff --git a/nmigen_soc/test/test_csr_bus.py b/nmigen_soc/test/test_csr_bus.py
index 83e9b7c1b32e48ded179232853c14958a2b8dc74..3d530c17695ba37e92f2f8d5b4fa1fe6a6291fda 100644 (file)
--- a/nmigen_soc/test/test_csr_bus.py
+++ b/nmigen_soc/test/test_csr_bus.py
@@ -56,7 +56,8 @@ class ElementTestCase(unittest.TestCase):
 
     def test_access_wrong(self):
         with self.assertRaisesRegex(ValueError,
-                r"Access mode must be one of \"r\", \"w\", or \"rw\", not 'wo'"):
+                r"Access mode must be one of \"r\", \"w\", "
+                r"or \"rw\", not 'wo'"):
             Element(1, "wo")
 
 
@@ -271,7 +272,8 @@ class DecoderTestCase(unittest.TestCase):
 
     def test_add_wrong_sub_bus(self):
         with self.assertRaisesRegex(TypeError,
-                r"Subordinate bus must be an instance of csr\.Interface, not 1"):
+                r"Subordinate bus must be an instance of "
+                r"csr\.Interface, not 1"):
             self.dut.add(1)
 
     def test_add_wrong_data_width(self):