more whitespace cleanup

[nmigen-soc.git] / nmigen_soc / test / test_csr_bus.py

diff --git a/nmigen_soc/test/test_csr_bus.py b/nmigen_soc/test/test_csr_bus.py
index 12fb58098a87402589a9c24bb31a1ad24888afc5..3d530c17695ba37e92f2f8d5b4fa1fe6a6291fda 100644 (file)
--- a/nmigen_soc/test/test_csr_bus.py
+++ b/nmigen_soc/test/test_csr_bus.py
@@ -38,7 +38,7 @@ class ElementTestCase(unittest.TestCase):
             ("w_stb", 1),
         ]))
 
-    def test_layout_0_rw(self): # degenerate but legal case
+    def test_layout_0_rw(self):  # degenerate but legal case
         elem = Element(0, access=Element.Access.RW)
         self.assertEqual(elem.width, 0)
         self.assertEqual(elem.access, Element.Access.RW)
@@ -56,7 +56,8 @@ class ElementTestCase(unittest.TestCase):
 
     def test_access_wrong(self):
         with self.assertRaisesRegex(ValueError,
-                r"Access mode must be one of \"r\", \"w\", or \"rw\", not 'wo'"):
+                r"Access mode must be one of \"r\", \"w\", "
+                r"or \"rw\", not 'wo'"):
             Element(1, "wo")
 
 
@@ -66,11 +67,11 @@ class InterfaceTestCase(unittest.TestCase):
         self.assertEqual(iface.addr_width, 12)
         self.assertEqual(iface.data_width, 8)
         self.assertEqual(iface.layout, Layout.cast([
-            ("addr",    12),
-            ("r_data",  8),
-            ("r_stb",   1),
-            ("w_data",  8),
-            ("w_stb",   1),
+            ("addr", 12),
+            ("r_data", 8),
+            ("r_stb", 1),
+            ("w_data", 8),
+            ("w_stb", 1),
         ]))
 
     def test_wrong_addr_width(self):
@@ -152,7 +153,7 @@ class MultiplexerTestCase(unittest.TestCase):
             self.assertEqual((yield elem_4_r.r_stb), 0)
             self.assertEqual((yield elem_16_rw.r_stb), 1)
             yield
-            yield bus.addr.eq(3) # pipeline a read
+            yield bus.addr.eq(3)  # pipeline a read
             self.assertEqual((yield bus.r_data), 0xa5)
 
             yield bus.r_stb.eq(1)
@@ -168,7 +169,7 @@ class MultiplexerTestCase(unittest.TestCase):
             yield bus.w_stb.eq(1)
             yield
             yield bus.w_stb.eq(0)
-            yield bus.addr.eq(2) # change address
+            yield bus.addr.eq(2)  # change address
             yield
             self.assertEqual((yield elem_8_w.w_stb), 1)
             self.assertEqual((yield elem_8_w.w_data), 0x3d)
@@ -182,7 +183,7 @@ class MultiplexerTestCase(unittest.TestCase):
             yield
             self.assertEqual((yield elem_8_w.w_stb), 0)
             self.assertEqual((yield elem_16_rw.w_stb), 0)
-            yield bus.addr.eq(3) # pipeline a write
+            yield bus.addr.eq(3)  # pipeline a write
             yield bus.w_data.eq(0xaa)
             yield
             self.assertEqual((yield elem_8_w.w_stb), 0)
@@ -271,12 +272,13 @@ class DecoderTestCase(unittest.TestCase):
 
     def test_add_wrong_sub_bus(self):
         with self.assertRaisesRegex(TypeError,
-               r"Subordinate bus must be an instance of csr\.Interface, not 1"):
+                r"Subordinate bus must be an instance of "
+                r"csr\.Interface, not 1"):
             self.dut.add(1)
 
     def test_add_wrong_data_width(self):
         mux = Multiplexer(addr_width=10, data_width=16)
-        Fragment.get(mux, platform=None) # silence UnusedElaboratable
+        Fragment.get(mux, platform=None)  # silence UnusedElaboratable
 
         with self.assertRaisesRegex(ValueError,
                 r"Subordinate bus has data width 16, which is not the same as "
@@ -284,12 +286,12 @@ class DecoderTestCase(unittest.TestCase):
             self.dut.add(mux.bus)
 
     def test_sim(self):
-        mux_1  = Multiplexer(addr_width=10, data_width=8)
+        mux_1 = Multiplexer(addr_width=10, data_width=8)
         self.dut.add(mux_1.bus)
         elem_1 = Element(8, "rw")
         mux_1.add(elem_1)
 
-        mux_2  = Multiplexer(addr_width=10, data_width=8)
+        mux_2 = Multiplexer(addr_width=10, data_width=8)
         self.dut.add(mux_2.bus)
         elem_2 = Element(8, "rw")
         mux_2.add(elem_2, addr=2)