def test_access_wrong(self):
with self.assertRaisesRegex(ValueError,
- r"Access mode must be one of \"r\", \"w\", or \"rw\", not 'wo'"):
+ r"Access mode must be one of \"r\", \"w\", "
+ r"or \"rw\", not 'wo'"):
Element(1, "wo")
def test_add_wrong_sub_bus(self):
with self.assertRaisesRegex(TypeError,
- r"Subordinate bus must be an instance of csr\.Interface, not 1"):
+ r"Subordinate bus must be an instance of "
+ r"csr\.Interface, not 1"):
self.dut.add(1)
def test_add_wrong_data_width(self):