resolve internal (nmigen_soc) imports

[nmigen-soc.git] / nmigen_soc / wishbone / bus.py

diff --git a/nmigen_soc/wishbone/bus.py b/nmigen_soc/wishbone/bus.py
index 37ce285b686dbd0915903c98d7a5d247197548b7..013ef7e2374a6481472d395c6c67eba71bf2958d 100644 (file)
--- a/nmigen_soc/wishbone/bus.py
+++ b/nmigen_soc/wishbone/bus.py
@@ -3,8 +3,8 @@ from nmigen import Record, Elaboratable, Module, Signal, Cat, Repl
 from nmigen.hdl.rec import Direction
 from nmigen.utils import log2_int
 
-from ..memory import MemoryMap
-from ..scheduler import *
+from nmigen_soc.memory import MemoryMap
+from nmigen_soc.scheduler import RoundRobin
 
 
 __all__ = ["CycleType", "BurstTypeExt", "Interface", "Decoder",