wrport.addr.eq(self.bus.adr[:len(rdport.addr)]),
wrport.data.eq(self.bus.dat_w)
]
- for i in range(4):
+ n_wrport = wrport.en.shape()[0]
+ n_bussel = self.bus.sel.shape()[0]
+ assert n_wrport == n_bussel, "bus enable count %d " \
+ "must match memory wen count %d" % (n_wrport, n_bussel)
+ for i in range(n_wrport):
m.d.comb += wrport.en[i].eq(self.bus.cyc & self.bus.stb &
self.bus.we & self.bus.sel[i])