more whitespace cleanup

[nmigen-soc.git] / nmigen_soc / wishbone / sram.py

diff --git a/nmigen_soc/wishbone/sram.py b/nmigen_soc/wishbone/sram.py
index eeeada3cc99c97c4eb246f2d3c7612a7b1bba5e2..ac5f12b32837f30900471ee01b227248d56f74c8 100644 (file)
--- a/nmigen_soc/wishbone/sram.py
+++ b/nmigen_soc/wishbone/sram.py
@@ -44,6 +44,7 @@ class SRAM(Elaboratable):
         The Wishbone bus interface providing access to the read/write
         ports of the memory.
     """
+
     def __init__(self, memory, read_only=False, bus=None,
                  granularity=None, features=frozenset()):
         if not isinstance(memory, Memory):
@@ -52,7 +53,8 @@ class SRAM(Elaboratable):
         self.memory = memory
         self.read_only = read_only
         if bus is None:
-            bus = Interface(addr_width=log2_int(self.memory.depth, need_pow2=False),
+            bus = Interface(addr_width=log2_int(self.memory.depth,
+                                                need_pow2=False),
                             data_width=self.memory.width,
                             granularity=granularity,
                             features=features,
@@ -76,7 +78,8 @@ class SRAM(Elaboratable):
 
         # write
         if not self.read_only:
-            m.submodules.wrport = wrport = self.memory.write_port(granularity=self.granularity)
+            m.submodules.wrport = wrport = self.memory.write_port(
+                granularity=self.granularity)
             m.d.comb += [
                 wrport.addr.eq(self.bus.adr[:len(rdport.addr)]),
                 wrport.data.eq(self.bus.dat_w)