The Wishbone bus interface providing access to the read/write
ports of the memory.
"""
+
def __init__(self, memory, read_only=False, bus=None,
granularity=None, features=frozenset()):
if not isinstance(memory, Memory):
self.memory = memory
self.read_only = read_only
if bus is None:
- bus = Interface(addr_width=log2_int(self.memory.depth, need_pow2=False),
+ bus = Interface(addr_width=log2_int(self.memory.depth,
+ need_pow2=False),
data_width=self.memory.width,
granularity=granularity,
features=features,
# write
if not self.read_only:
- m.submodules.wrport = wrport = self.memory.write_port(granularity=self.granularity)
+ m.submodules.wrport = wrport = self.memory.write_port(
+ granularity=self.granularity)
m.d.comb += [
wrport.addr.eq(self.bus.adr[:len(rdport.addr)]),
wrport.data.eq(self.bus.dat_w)