wrport.addr.eq(self.bus.adr[:len(rdport.addr)]),
wrport.data.eq(self.bus.dat_w)
]
- n_wrport = wrport.en.shape()[0]
- n_bussel = self.bus.sel.shape()[0]
+ n_wrport = wrport.en.width
+ n_bussel = self.bus.sel.width
assert n_wrport == n_bussel, "bus enable count %d " \
"must match memory wen count %d" % (n_wrport, n_bussel)
wen = Signal()