X-Git-Url: https://git.libre-soc.org/?p=nmigen-soc.git;a=blobdiff_plain;f=nmigen_soc%2Fwishbone%2Fsram.py;h=ac5f12b32837f30900471ee01b227248d56f74c8;hp=c5a139df41f1533ea40a63bfff1d78017afd55a9;hb=c5e68f0aea252654ca196574b5396a23036f3f2d;hpb=0b0d56ef5a3123cc981ab629330a996e9d3a503a

diff --git a/nmigen_soc/wishbone/sram.py b/nmigen_soc/wishbone/sram.py
index c5a139d..ac5f12b 100644
--- a/nmigen_soc/wishbone/sram.py
+++ b/nmigen_soc/wishbone/sram.py
@@ -53,7 +53,8 @@ class SRAM(Elaboratable):
         self.memory = memory
         self.read_only = read_only
         if bus is None:
-            bus = Interface(addr_width=log2_int(self.memory.depth, need_pow2=False),
+            bus = Interface(addr_width=log2_int(self.memory.depth,
+                                                need_pow2=False),
                             data_width=self.memory.width,
                             granularity=granularity,
                             features=features,