resolve internal (nmigen_soc) imports
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 20 Jun 2020 00:22:59 +0000 (01:22 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 20 Jun 2020 00:22:59 +0000 (01:22 +0100)
commit0d0ea2c843a8035d2e88181930cd38af6a2ab31d
treeec146d205501482053b0870e98f96020f4354508
parent5cd5d13c36e18d04f084d48ff1e9d9a997a140e9
resolve internal (nmigen_soc) imports
nmigen_soc/csr/__init__.py
nmigen_soc/csr/bus.py
nmigen_soc/csr/wishbone.py
nmigen_soc/test/test_csr_bus.py
nmigen_soc/test/test_csr_wishbone.py
nmigen_soc/test/test_memory.py
nmigen_soc/test/test_wishbone_bus.py
nmigen_soc/wishbone/__init__.py
nmigen_soc/wishbone/bus.py
nmigen_soc/wishbone/sram.py