csr.bus: add Multiplexer.
authorwhitequark <whitequark@whitequark.org>
Fri, 25 Oct 2019 20:06:23 +0000 (20:06 +0000)
committerwhitequark <whitequark@whitequark.org>
Fri, 25 Oct 2019 20:06:23 +0000 (20:06 +0000)
commit2a634b3a43739d024ff1f57c1d35aa891a47e3dc
treec49e9091edd0edd1244cfc6c4a47e2db79f4354b
parent120ea5387c8598d69d9e81752949212f80305a43
csr.bus: add Multiplexer.
nmigen_soc/csr/bus.py
nmigen_soc/memory.py
nmigen_soc/test/test_csr_bus.py