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resolve internal (nmigen_soc) imports
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 20 Jun 2020 00:22:59 +0000
(
01:22
+0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 20 Jun 2020 00:22:59 +0000
(
01:22
+0100)
nmigen_soc/csr/__init__.py
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nmigen_soc/csr/bus.py
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nmigen_soc/csr/wishbone.py
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nmigen_soc/test/test_csr_bus.py
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nmigen_soc/test/test_csr_wishbone.py
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nmigen_soc/test/test_memory.py
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nmigen_soc/test/test_wishbone_bus.py
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nmigen_soc/wishbone/__init__.py
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nmigen_soc/wishbone/bus.py
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nmigen_soc/wishbone/sram.py
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diff --git
a/nmigen_soc/csr/__init__.py
b/nmigen_soc/csr/__init__.py
index 3b2d416b27c5bdc68e6bc6b972212eaf9c7469ca..f644b89fe09c8219bad11efcaf3169bbbe3efd51 100644
(file)
--- a/
nmigen_soc/csr/__init__.py
+++ b/
nmigen_soc/csr/__init__.py
@@
-1
+1
@@
-from
.bus import *
+from
nmigen_soc.csr.bus import Element, Interface, Decoder, Multiplexer
diff --git
a/nmigen_soc/csr/bus.py
b/nmigen_soc/csr/bus.py
index 4c6c6ac98618febe8ea58191b2d4276e2662dfe1..91e9930e84f4c8b6e9980b7ff4f138ead4fa43c3 100644
(file)
--- a/
nmigen_soc/csr/bus.py
+++ b/
nmigen_soc/csr/bus.py
@@
-2,7
+2,7
@@
import enum
from nmigen import Record, Elaboratable, Module, Signal, Mux
from nmigen.utils import log2_int
from nmigen import Record, Elaboratable, Module, Signal, Mux
from nmigen.utils import log2_int
-from
.
.memory import MemoryMap
+from
nmigen_soc
.memory import MemoryMap
__all__ = ["Element", "Interface", "Decoder", "Multiplexer"]
__all__ = ["Element", "Interface", "Decoder", "Multiplexer"]
diff --git
a/nmigen_soc/csr/wishbone.py
b/nmigen_soc/csr/wishbone.py
index 54e3f490ba1ee4b1fe11f1b14c624aaa3af80d6b..2d562390b5449484decf73f12928e4a2effc7f6b 100644
(file)
--- a/
nmigen_soc/csr/wishbone.py
+++ b/
nmigen_soc/csr/wishbone.py
@@
-1,8
+1,8
@@
from nmigen import Elaboratable, Module, Signal, Cat
from nmigen.utils import log2_int
from nmigen import Elaboratable, Module, Signal, Cat
from nmigen.utils import log2_int
-from
.
import Interface as CSRInterface
-from
.
.wishbone import Interface as WishboneInterface
+from
nmigen_soc.csr.bus
import Interface as CSRInterface
+from
nmigen_soc
.wishbone import Interface as WishboneInterface
__all__ = ["WishboneCSRBridge"]
__all__ = ["WishboneCSRBridge"]
diff --git
a/nmigen_soc/test/test_csr_bus.py
b/nmigen_soc/test/test_csr_bus.py
index e53331839a316ec7648fa15e6406a2fded36caca..36d46e30e67711016f3a7826bd7e26ca3e865115 100644
(file)
--- a/
nmigen_soc/test/test_csr_bus.py
+++ b/
nmigen_soc/test/test_csr_bus.py
@@
-5,7
+5,7
@@
from nmigen import Record, Module
from nmigen.hdl.rec import Layout
from nmigen.back.pysim import Simulator, Fragment
from nmigen.hdl.rec import Layout
from nmigen.back.pysim import Simulator, Fragment
-from
..csr.bus import *
+from
nmigen_soc.csr.bus import Element, Interface, Decoder, Multiplexer
class ElementTestCase(unittest.TestCase):
class ElementTestCase(unittest.TestCase):
diff --git
a/nmigen_soc/test/test_csr_wishbone.py
b/nmigen_soc/test/test_csr_wishbone.py
index adfa590ed80ec2cbd966e9f4293a0afdb10ac261..2cde268d2b2075d62a54fe7c382a3c65287f6118 100644
(file)
--- a/
nmigen_soc/test/test_csr_wishbone.py
+++ b/
nmigen_soc/test/test_csr_wishbone.py
@@
-4,8
+4,8
@@
import unittest
from nmigen import Elaboratable, Signal, Module
from nmigen.back.pysim import Simulator, Fragment
from nmigen import Elaboratable, Signal, Module
from nmigen.back.pysim import Simulator, Fragment
-from
..
import csr
-from
..csr.wishbone import *
+from
nmigen_soc
import csr
+from
nmigen_soc.csr.wishbone import WishboneCSRBridge
class MockRegister(Elaboratable):
class MockRegister(Elaboratable):
diff --git
a/nmigen_soc/test/test_memory.py
b/nmigen_soc/test/test_memory.py
index 7f42319f0e8b7a310d690804da8cc27956358b4d..1b320ef0f869a7e1bb2b64cb4d6542413f12d31f 100644
(file)
--- a/
nmigen_soc/test/test_memory.py
+++ b/
nmigen_soc/test/test_memory.py
@@
-1,6
+1,6
@@
import unittest
import unittest
-from
.
.memory import _RangeMap, MemoryMap
+from
nmigen_soc
.memory import _RangeMap, MemoryMap
class RangeMapTestCase(unittest.TestCase):
class RangeMapTestCase(unittest.TestCase):
diff --git
a/nmigen_soc/test/test_wishbone_bus.py
b/nmigen_soc/test/test_wishbone_bus.py
index 1e63155750d8e504c102a5a47a85b2890f8f1598..fe7aacf393cc3e60ebe6787cb483a8c1c07ec039 100644
(file)
--- a/
nmigen_soc/test/test_wishbone_bus.py
+++ b/
nmigen_soc/test/test_wishbone_bus.py
@@
-5,7
+5,9
@@
from nmigen import Module, Record, Elaboratable
from nmigen.hdl.rec import Layout, DIR_FANOUT, DIR_FANIN
from nmigen.back.pysim import Simulator, Delay, Tick
from nmigen.hdl.rec import Layout, DIR_FANOUT, DIR_FANIN
from nmigen.back.pysim import Simulator, Delay, Tick
-from ..wishbone import *
+from nmigen_soc.wishbone import (Interface, CycleType, Decoder,
+ InterconnectShared,
+ Arbiter, BurstTypeExt)
class InterfaceTestCase(unittest.TestCase):
class InterfaceTestCase(unittest.TestCase):
diff --git
a/nmigen_soc/wishbone/__init__.py
b/nmigen_soc/wishbone/__init__.py
index 4a197f74c7d54d60b4ff79795a978c7a1cd2f07e..9e567ac97125c5c3b4b003f2a8251ade86e3df17 100644
(file)
--- a/
nmigen_soc/wishbone/__init__.py
+++ b/
nmigen_soc/wishbone/__init__.py
@@
-1,2
+1,3
@@
-from .bus import *
-from .sram import *
+from nmigen_soc.wishbone.bus import (Interface, CycleType, Decoder,
+ InterconnectShared, Arbiter,
+ BurstTypeExt)
diff --git
a/nmigen_soc/wishbone/bus.py
b/nmigen_soc/wishbone/bus.py
index 37ce285b686dbd0915903c98d7a5d247197548b7..013ef7e2374a6481472d395c6c67eba71bf2958d 100644
(file)
--- a/
nmigen_soc/wishbone/bus.py
+++ b/
nmigen_soc/wishbone/bus.py
@@
-3,8
+3,8
@@
from nmigen import Record, Elaboratable, Module, Signal, Cat, Repl
from nmigen.hdl.rec import Direction
from nmigen.utils import log2_int
from nmigen.hdl.rec import Direction
from nmigen.utils import log2_int
-from
.
.memory import MemoryMap
-from
..scheduler import *
+from
nmigen_soc
.memory import MemoryMap
+from
nmigen_soc.scheduler import RoundRobin
__all__ = ["CycleType", "BurstTypeExt", "Interface", "Decoder",
__all__ = ["CycleType", "BurstTypeExt", "Interface", "Decoder",
diff --git
a/nmigen_soc/wishbone/sram.py
b/nmigen_soc/wishbone/sram.py
index f6734b2ef40c6407867d44df2caa8991619e1b05..ffb8f63da0c3a84cad1391deba5eeb363fdad8ef 100644
(file)
--- a/
nmigen_soc/wishbone/sram.py
+++ b/
nmigen_soc/wishbone/sram.py
@@
-1,7
+1,7
@@
from nmigen import Elaboratable, Memory, Module
from nmigen.utils import log2_int
from nmigen import Elaboratable, Memory, Module
from nmigen.utils import log2_int
-from .bus import Interface
+from
nmigen.wishbone
.bus import Interface
__all__ = ["SRAM"]
__all__ = ["SRAM"]