Add missing tests (100% branch coverage!)

Found several bugs, too.

diff --git a/nmigen_soc/memory.py b/nmigen_soc/memory.py
index 7601781abbc15e612e571a1030dd5d918ad20487..c7214e0e4eed34a00f5ec56beda101c2d4e38eee 100644 (file)
--- a/nmigen_soc/memory.py
+++ b/nmigen_soc/memory.py
@@ -151,8 +151,9 @@ class MemoryMap:
                     overlap_descrs.append("resource {!r} at {:#x}..{:#x}"
                         .format(overlap, resource_range.start, resource_range.stop))
                 if overlap in self._windows:
+                    window_range = self._windows[overlap]
                     overlap_descrs.append("window {!r} at {:#x}..{:#x}"
-                        .format(overlap, resource_range.start, resource_range.stop))
+                        .format(overlap, window_range.start, window_range.stop))
             raise ValueError("Address range {:#x}..{:#x} overlaps with {}"
                              .format(addr, addr + size, ", ".join(overlap_descrs)))
 
@@ -351,7 +352,7 @@ class MemoryMap:
                 for sub_resource, sub_descr in assignment.all_resources():
                     yield sub_resource, self._translate(*sub_descr, assignment, addr_range)
             else:
-                assert False
+                assert False # :nocov:
 
     def find_resource(self, resource):
         """Find address range corresponding to a resource.
@@ -409,4 +410,4 @@ class MemoryMap:
             addr_range = self._windows[assignment]
             return assignment.decode_address((address - addr_range.start) // addr_range.step)
         else:
-            assert False
+            assert False # :nocov:

diff --git a/nmigen_soc/test/test_csr_bus.py b/nmigen_soc/test/test_csr_bus.py
index d88912868074148434e135e4f75292394c331007..85115a9fd846c48b087b85e57ef87ccb54ca4cda 100644 (file)
--- a/nmigen_soc/test/test_csr_bus.py
+++ b/nmigen_soc/test/test_csr_bus.py
@@ -110,9 +110,9 @@ class MultiplexerTestCase(unittest.TestCase):
                          (2, 3))
 
     def test_add_wrong(self):
-        with self.assertRaisesRegex(ValueError,
-                r"Width must be a non-negative integer, not -1"):
-            Element(-1, "rw")
+        with self.assertRaisesRegex(TypeError,
+                r"Element must be an instance of csr\.Element, not 'foo'"):
+            self.dut.add("foo")
 
     def test_align_to(self):
         self.assertEqual(self.dut.add(Element(8, "rw")),
@@ -263,6 +263,13 @@ class DecoderTestCase(unittest.TestCase):
         self.dut = Decoder(addr_width=16, data_width=8)
         Fragment.get(self.dut, platform=None) # silence UnusedElaboratable
 
+    def test_align_to(self):
+        self.assertEqual(self.dut.add(Interface(addr_width=10, data_width=8)),
+                         (0, 0x400, 1))
+        self.assertEqual(self.dut.align_to(12), 0x1000)
+        self.assertEqual(self.dut.add(Interface(addr_width=10, data_width=8)),
+                         (0x1000, 0x1400, 1))
+
     def test_add_wrong_sub_bus(self):
         with self.assertRaisesRegex(TypeError,
                 r"Subordinate bus must be an instance of csr\.Interface, not 1"):

diff --git a/nmigen_soc/test/test_memory.py b/nmigen_soc/test/test_memory.py
index 5821c6e0f8fbb4879a3ec5c157d0e04973ee5811..bc5a1ceefe873231e2834104a124da8da7a37097 100644 (file)
--- a/nmigen_soc/test/test_memory.py
+++ b/nmigen_soc/test/test_memory.py
@@ -181,6 +181,23 @@ class MemoryMapTestCase(unittest.TestCase):
                 r"16 is not an integer multiple of window data width 7"):
             memory_map.add_window(MemoryMap(addr_width=10, data_width=7), sparse=False)
 
+    def test_add_window_wrong_overlap(self):
+        memory_map = MemoryMap(addr_width=16, data_width=8)
+        memory_map.add_window(MemoryMap(addr_width=10, data_width=8))
+        with self.assertRaisesRegex(ValueError,
+                r"Address range 0x200\.\.0x600 overlaps with window "
+                r"<nmigen_soc\.memory\.MemoryMap object at .+?> at 0x0\.\.0x400"):
+            memory_map.add_window(MemoryMap(addr_width=10, data_width=8), addr=0x200)
+
+    def test_add_window_wrong_twice(self):
+        memory_map = MemoryMap(addr_width=16, data_width=8)
+        window = MemoryMap(addr_width=10, data_width=8)
+        memory_map.add_window(window)
+        with self.assertRaisesRegex(ValueError,
+                r"Window <nmigen_soc\.memory\.MemoryMap object at .+?> is already added "
+                r"at address range 0x0\.\.0x400"):
+            memory_map.add_window(window)
+
     def test_iter_windows(self):
         memory_map = MemoryMap(addr_width=16, data_width=16)
         window_1 = MemoryMap(addr_width=10, data_width=8)
@@ -198,6 +215,12 @@ class MemoryMapTestCase(unittest.TestCase):
         self.assertEqual(memory_map.align_to(10), 0x400)
         self.assertEqual(memory_map.add_resource("b", size=16), (0x400, 0x410))
 
+    def test_align_to_wrong(self):
+        memory_map = MemoryMap(addr_width=16, data_width=8)
+        with self.assertRaisesRegex(ValueError,
+                r"Alignment must be a non-negative integer, not -1"):
+            memory_map.align_to(-1)
+
 
 class MemoryMapDiscoveryTestCase(unittest.TestCase):
     def setUp(self):

diff --git a/nmigen_soc/test/test_wishbone_bus.py b/nmigen_soc/test/test_wishbone_bus.py
index 0c8b6d847b20c7c0cc9fa90af3074fdd89985f94..00da53012c51bb942962df4a358be76f297374b3 100644 (file)
--- a/nmigen_soc/test/test_wishbone_bus.py
+++ b/nmigen_soc/test/test_wishbone_bus.py
@@ -76,7 +76,7 @@ class InterfaceTestCase(unittest.TestCase):
                 r"Granularity must be one of 8, 16, 32, 64, not 7"):
             Interface(addr_width=0, data_width=32, granularity=7)
 
-    def test_wrong_granularity(self):
+    def test_wrong_granularity_wide(self):
         with self.assertRaisesRegex(ValueError,
                 r"Granularity 32 may not be greater than data width 8"):
             Interface(addr_width=0, data_width=8, granularity=32)