test in sram for deliberately delaying response
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 4 Aug 2020 18:29:59 +0000 (19:29 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 4 Aug 2020 18:29:59 +0000 (19:29 +0100)
nmigen_soc/wishbone/sram.py

index dbb7615..22b0efd 100644 (file)
@@ -98,6 +98,13 @@ class SRAM(Elaboratable):
         # generate ack
         m.d.sync += self.bus.ack.eq(0)
         with m.If(self.bus.cyc & self.bus.stb & ~self.bus.ack):
-            m.d.sync += self.bus.ack.eq(1)
+            if False: # test which deliberately delays response
+                counter = Signal(3)
+                m.d.sync += counter.eq(counter + 1)
+                with m.If(counter == 7):
+                    m.d.sync += self.bus.ack.eq(1)
+                    m.d.sync += counter.eq(0)
+            else:
+                m.d.sync += self.bus.ack.eq(1)
 
         return m