From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 20 Jun 2020 00:22:59 +0000 (+0100)
Subject: resolve internal (nmigen_soc) imports
X-Git-Tag: 24jan2021_ls180~9
X-Git-Url: https://git.libre-soc.org/?p=nmigen-soc.git;a=commitdiff_plain;h=0d0ea2c843a8035d2e88181930cd38af6a2ab31d

resolve internal (nmigen_soc) imports
---

diff --git a/nmigen_soc/csr/__init__.py b/nmigen_soc/csr/__init__.py
index 3b2d416..f644b89 100644
--- a/nmigen_soc/csr/__init__.py
+++ b/nmigen_soc/csr/__init__.py
@@ -1 +1 @@
-from .bus import *
+from nmigen_soc.csr.bus import Element, Interface, Decoder, Multiplexer
diff --git a/nmigen_soc/csr/bus.py b/nmigen_soc/csr/bus.py
index 4c6c6ac..91e9930 100644
--- a/nmigen_soc/csr/bus.py
+++ b/nmigen_soc/csr/bus.py
@@ -2,7 +2,7 @@ import enum
 from nmigen import Record, Elaboratable, Module, Signal, Mux
 from nmigen.utils import log2_int
 
-from ..memory import MemoryMap
+from nmigen_soc.memory import MemoryMap
 
 
 __all__ = ["Element", "Interface", "Decoder", "Multiplexer"]
diff --git a/nmigen_soc/csr/wishbone.py b/nmigen_soc/csr/wishbone.py
index 54e3f49..2d56239 100644
--- a/nmigen_soc/csr/wishbone.py
+++ b/nmigen_soc/csr/wishbone.py
@@ -1,8 +1,8 @@
 from nmigen import Elaboratable, Module, Signal, Cat
 from nmigen.utils import log2_int
 
-from . import Interface as CSRInterface
-from ..wishbone import Interface as WishboneInterface
+from nmigen_soc.csr.bus import Interface as CSRInterface
+from nmigen_soc.wishbone import Interface as WishboneInterface
 
 
 __all__ = ["WishboneCSRBridge"]
diff --git a/nmigen_soc/test/test_csr_bus.py b/nmigen_soc/test/test_csr_bus.py
index e533318..36d46e3 100644
--- a/nmigen_soc/test/test_csr_bus.py
+++ b/nmigen_soc/test/test_csr_bus.py
@@ -5,7 +5,7 @@ from nmigen import Record, Module
 from nmigen.hdl.rec import Layout
 from nmigen.back.pysim import Simulator, Fragment
 
-from ..csr.bus import *
+from nmigen_soc.csr.bus import Element, Interface, Decoder, Multiplexer
 
 
 class ElementTestCase(unittest.TestCase):
diff --git a/nmigen_soc/test/test_csr_wishbone.py b/nmigen_soc/test/test_csr_wishbone.py
index adfa590..2cde268 100644
--- a/nmigen_soc/test/test_csr_wishbone.py
+++ b/nmigen_soc/test/test_csr_wishbone.py
@@ -4,8 +4,8 @@ import unittest
 from nmigen import Elaboratable, Signal, Module
 from nmigen.back.pysim import Simulator, Fragment
 
-from .. import csr
-from ..csr.wishbone import *
+from nmigen_soc import csr
+from nmigen_soc.csr.wishbone import WishboneCSRBridge
 
 
 class MockRegister(Elaboratable):
diff --git a/nmigen_soc/test/test_memory.py b/nmigen_soc/test/test_memory.py
index 7f42319..1b320ef 100644
--- a/nmigen_soc/test/test_memory.py
+++ b/nmigen_soc/test/test_memory.py
@@ -1,6 +1,6 @@
 import unittest
 
-from ..memory import _RangeMap, MemoryMap
+from nmigen_soc.memory import _RangeMap, MemoryMap
 
 
 class RangeMapTestCase(unittest.TestCase):
diff --git a/nmigen_soc/test/test_wishbone_bus.py b/nmigen_soc/test/test_wishbone_bus.py
index 1e63155..fe7aacf 100644
--- a/nmigen_soc/test/test_wishbone_bus.py
+++ b/nmigen_soc/test/test_wishbone_bus.py
@@ -5,7 +5,9 @@ from nmigen import Module, Record, Elaboratable
 from nmigen.hdl.rec import Layout, DIR_FANOUT, DIR_FANIN
 from nmigen.back.pysim import Simulator, Delay, Tick
 
-from ..wishbone import *
+from nmigen_soc.wishbone import (Interface, CycleType, Decoder,
+                                 InterconnectShared,
+                                 Arbiter, BurstTypeExt)
 
 
 class InterfaceTestCase(unittest.TestCase):
diff --git a/nmigen_soc/wishbone/__init__.py b/nmigen_soc/wishbone/__init__.py
index 4a197f7..9e567ac 100644
--- a/nmigen_soc/wishbone/__init__.py
+++ b/nmigen_soc/wishbone/__init__.py
@@ -1,2 +1,3 @@
-from .bus import *
-from .sram import *
+from nmigen_soc.wishbone.bus import (Interface, CycleType, Decoder,
+                                     InterconnectShared, Arbiter,
+                                     BurstTypeExt)
diff --git a/nmigen_soc/wishbone/bus.py b/nmigen_soc/wishbone/bus.py
index 37ce285..013ef7e 100644
--- a/nmigen_soc/wishbone/bus.py
+++ b/nmigen_soc/wishbone/bus.py
@@ -3,8 +3,8 @@ from nmigen import Record, Elaboratable, Module, Signal, Cat, Repl
 from nmigen.hdl.rec import Direction
 from nmigen.utils import log2_int
 
-from ..memory import MemoryMap
-from ..scheduler import *
+from nmigen_soc.memory import MemoryMap
+from nmigen_soc.scheduler import RoundRobin
 
 
 __all__ = ["CycleType", "BurstTypeExt", "Interface", "Decoder",
diff --git a/nmigen_soc/wishbone/sram.py b/nmigen_soc/wishbone/sram.py
index f6734b2..ffb8f63 100644
--- a/nmigen_soc/wishbone/sram.py
+++ b/nmigen_soc/wishbone/sram.py
@@ -1,7 +1,7 @@
 from nmigen import Elaboratable, Memory, Module
 from nmigen.utils import log2_int
 
-from .bus import Interface
+from nmigen.wishbone.bus import Interface
 
 
 __all__ = ["SRAM"]