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[nmigen-soc.git] / nmigen_soc / wishbone / sram.py

2020-10-01	Luke Kenneth Casso...	must not delay ack to wb request in SRAM master 24jan2021_ls180	commit \| commitdiff
2020-08-04	Luke Kenneth Casso...	test in sram for deliberately delaying response	commit \| commitdiff
2020-07-19	Luke Kenneth Casso...	cannot use shape()[0] - must use width property	commit \| commitdiff
2020-06-26	Luke Kenneth Casso...	write-enable sram into common wen signal, use that...	commit \| commitdiff
2020-06-20	Luke Kenneth Casso...	add assertion checking bus write against memory write...	commit \| commitdiff
2020-06-20	Luke Kenneth Casso...	avoid looking like a singleton pattern	commit \| commitdiff
2020-06-20	Luke Kenneth Casso...	spelling correctinos	commit \| commitdiff
2020-06-20	Luke Kenneth Casso...	import error	commit \| commitdiff
2020-06-20	Luke Kenneth Casso...	resolve internal (nmigen_soc) imports	commit \| commitdiff
2020-06-20	Luke Kenneth Casso...	fix nmigen imports	commit \| commitdiff
2020-06-19	Luke Kenneth Casso...	more whitespace cleanup	commit \| commitdiff
2020-06-19	Luke Kenneth Casso...	autopep8 cleanup	commit \| commitdiff
2020-06-19	Luke Kenneth Casso...	whitespace cleanup	commit \| commitdiff
2020-03-01	Harry Ho	wishbone: fix SRAM; improve tests for Decoder & Arbiter wishbone_interconnect	commit \| commitdiff
2020-01-30	Harry Ho	wishbone: fix docstring & unneeded parameter for Interc...	commit \| commitdiff
2020-01-29	Harry Ho	wishbone.bus: borrow & re-design Arbiter from 'jfng...	commit \| commitdiff
2020-01-29	Harry Ho	wishbone: optimise SRAM addr_width	commit \| commitdiff
2020-01-29	Harry Ho	wishbone: add Arbiter, RoundRobin, SRAM, InterconnectShared	commit \| commitdiff

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