git.libre-soc.org Git - nmigen-soc.git/history

[nmigen-soc.git] / nmigen_soc / wishbone / sram.py

2020-06-26	Luke Kenneth Casso...	write-enable sram into common wen signal, use that...	blob \| commitdiff \| raw
2020-06-20	Luke Kenneth Casso...	add assertion checking bus write against memory write...	blob \| commitdiff \| raw \| diff to current
2020-06-20	Luke Kenneth Casso...	avoid looking like a singleton pattern	blob \| commitdiff \| raw \| diff to current
2020-06-20	Luke Kenneth Casso...	spelling correctinos	blob \| commitdiff \| raw \| diff to current
2020-06-20	Luke Kenneth Casso...	import error	blob \| commitdiff \| raw \| diff to current
2020-06-20	Luke Kenneth Casso...	resolve internal (nmigen_soc) imports	blob \| commitdiff \| raw \| diff to current
2020-06-20	Luke Kenneth Casso...	fix nmigen imports	blob \| commitdiff \| raw \| diff to current
2020-06-19	Luke Kenneth Casso...	more whitespace cleanup	blob \| commitdiff \| raw \| diff to current
2020-06-19	Luke Kenneth Casso...	autopep8 cleanup	blob \| commitdiff \| raw \| diff to current
2020-06-19	Luke Kenneth Casso...	whitespace cleanup	blob \| commitdiff \| raw \| diff to current
2020-03-01	Harry Ho	wishbone: fix SRAM; improve tests for Decoder & Arbiter wishbone_interconnect	blob \| commitdiff \| raw \| diff to current
2020-01-30	Harry Ho	wishbone: fix docstring & unneeded parameter for Interc...	blob \| commitdiff \| raw \| diff to current
2020-01-29	Harry Ho	wishbone.bus: borrow & re-design Arbiter from 'jfng...	blob \| commitdiff \| raw \| diff to current
2020-01-29	Harry Ho	wishbone: optimise SRAM addr_width	blob \| commitdiff \| raw \| diff to current
2020-01-29	Harry Ho	wishbone: add Arbiter, RoundRobin, SRAM, InterconnectShared	blob \| commitdiff \| raw \| diff to current

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