nmigen-soc.git
13 months agowishbone: fix SRAM; improve tests for Decoder & Arbiter wishbone_interconnect
Harry Ho [Sun, 1 Mar 2020 04:17:10 +0000 (12:17 +0800)]
wishbone: fix SRAM; improve tests for Decoder & Arbiter

14 months agowishbone: fix docstring & unneeded parameter for InterconnectShared
Harry Ho [Wed, 29 Jan 2020 10:01:31 +0000 (18:01 +0800)]
wishbone: fix docstring & unneeded parameter for InterconnectShared

14 months agowishbone.bus: borrow & re-design Arbiter from 'jfng/wishbone-arbiter'
Harry Ho [Wed, 29 Jan 2020 07:19:49 +0000 (15:19 +0800)]
wishbone.bus: borrow & re-design Arbiter from 'jfng/wishbone-arbiter'
(credits to @jfng, commit 87281d1f48c9689323c411970870611e6dba1348)

14 months agowishbone: fix that RoundRobin might assert CYC indefinitely
Harry Ho [Wed, 29 Jan 2020 04:14:11 +0000 (12:14 +0800)]
wishbone: fix that RoundRobin might assert CYC indefinitely

14 months agowishbone: optimise SRAM addr_width
Harry Ho [Wed, 8 Jan 2020 06:39:43 +0000 (14:39 +0800)]
wishbone: optimise SRAM addr_width

14 months agowishbone: add a simple test for InterconnectShared
Harry Ho [Mon, 6 Jan 2020 02:26:28 +0000 (10:26 +0800)]
wishbone: add a simple test for InterconnectShared

14 months agowishbone: add Arbiter, RoundRobin, SRAM, InterconnectShared
Harry Ho [Fri, 20 Dec 2019 04:08:57 +0000 (12:08 +0800)]
wishbone: add Arbiter, RoundRobin, SRAM, InterconnectShared

14 months agowishbone.bus: add Arbiter.
Jean-François Nguyen [Wed, 22 Jan 2020 14:07:51 +0000 (15:07 +0100)]
wishbone.bus: add Arbiter.

17 months agowishbone.bus: add Decoder.
whitequark [Sat, 26 Oct 2019 07:54:02 +0000 (07:54 +0000)]
wishbone.bus: add Decoder.

17 months agomemory: add Memory.window_patterns(), to simplify decoders.
whitequark [Sat, 26 Oct 2019 02:52:49 +0000 (02:52 +0000)]
memory: add Memory.window_patterns(), to simplify decoders.

17 months agowishbone.bus.Interface: add support for LOCK_IO signal.
whitequark [Sat, 26 Oct 2019 02:40:18 +0000 (02:40 +0000)]
wishbone.bus.Interface: add support for LOCK_IO signal.

17 months agoTravis: set up CI builds and coverage.
whitequark [Sat, 26 Oct 2019 02:29:05 +0000 (02:29 +0000)]
Travis: set up CI builds and coverage.

17 months agoAdd missing tests (100% branch coverage!)
whitequark [Sat, 26 Oct 2019 02:25:45 +0000 (02:25 +0000)]
Add missing tests (100% branch coverage!)

Found several bugs, too.

17 months agocsr.wishbone: add WishboneCSRBridge.
whitequark [Fri, 25 Oct 2019 23:47:52 +0000 (23:47 +0000)]
csr.wishbone: add WishboneCSRBridge.

17 months agocsr.bus.Multiplexer: fix element w_stb getting stuck.
whitequark [Sat, 26 Oct 2019 00:58:27 +0000 (00:58 +0000)]
csr.bus.Multiplexer: fix element w_stb getting stuck.

Also, don't clear shadow; this would break e.g. reading a 64-bit
CSR register through a 32-bit Wishbone bus if a code fetch happens
between the halves. Instead, clear shadow enable flag driving OR-mux.

17 months agowishbone.bus: add Interface.
whitequark [Fri, 25 Oct 2019 21:22:59 +0000 (21:22 +0000)]
wishbone.bus: add Interface.

17 months agocsr.bus.{Multiplexer↔Decoder}
whitequark [Fri, 25 Oct 2019 21:30:46 +0000 (21:30 +0000)]
csr.bus.{Multiplexer↔Decoder}

This reverses the rename done in commit 5520e0d7. Commit 2a634b3a
introduced a Multiplexer that doesn't actually do multiplexing, so
revert that to make everything less confusing.

17 months agocsr.bus: add Multiplexer.
whitequark [Fri, 25 Oct 2019 20:06:23 +0000 (20:06 +0000)]
csr.bus: add Multiplexer.

17 months agotest: silence spurious warning.
whitequark [Fri, 25 Oct 2019 18:44:27 +0000 (18:44 +0000)]
test: silence spurious warning.

17 months agocsr.bus: rewrite using the MemoryMap abstraction.
whitequark [Fri, 25 Oct 2019 18:41:40 +0000 (18:41 +0000)]
csr.bus: rewrite using the MemoryMap abstraction.

17 months agomemory: add a first-class memory map abstraction.
whitequark [Fri, 25 Oct 2019 18:15:34 +0000 (18:15 +0000)]
memory: add a first-class memory map abstraction.

17 months agocsr.bus: use proper enum instead of ad-hoc string enumeration.
whitequark [Fri, 25 Oct 2019 10:54:49 +0000 (10:54 +0000)]
csr.bus: use proper enum instead of ad-hoc string enumeration.

17 months agocsr.bus: drop CSR prefix from class names.
whitequark [Fri, 25 Oct 2019 10:41:07 +0000 (10:41 +0000)]
csr.bus: drop CSR prefix from class names.

Application code should use Python imports similar to:

    from nmigen_soc import csr
    ...
    decoder = csr.Decoder(...)

thus achieving the same effect with less namespace pollution.

17 months agocsr.bus: split CSRMultiplexer to CSRInterface+CSRDecoder.
whitequark [Fri, 25 Oct 2019 10:37:03 +0000 (10:37 +0000)]
csr.bus: split CSRMultiplexer to CSRInterface+CSRDecoder.

17 months agocsr.bus: improve comments/docs. NFC.
whitequark [Tue, 22 Oct 2019 03:56:52 +0000 (03:56 +0000)]
csr.bus: improve comments/docs. NFC.

17 months agocsr.bus: add CSRElement and CSRMultiplexer.
whitequark [Mon, 21 Oct 2019 15:05:24 +0000 (15:05 +0000)]
csr.bus: add CSRElement and CSRMultiplexer.

17 months agoAdd __version__ boilerplate.
whitequark [Wed, 16 Oct 2019 15:31:26 +0000 (15:31 +0000)]
Add __version__ boilerplate.

17 months agosetup: update scm_version().
whitequark [Wed, 16 Oct 2019 15:29:13 +0000 (15:29 +0000)]
setup: update scm_version().

19 months agoInitial commit.
whitequark [Fri, 6 Sep 2019 08:58:19 +0000 (08:58 +0000)]
Initial commit.