hdl.ast,back.rtlil: implement Cover.

[nmigen.git] / nmigen / hdl / xfrm.py

diff --git a/nmigen/hdl/xfrm.py b/nmigen/hdl/xfrm.py
index 8793c5996d33ab544da82f2242366f1e0c21fd92..ab12ffdd3a46b914bdb5ca83ecf149758d583aa8 100644 (file)
--- a/nmigen/hdl/xfrm.py
+++ b/nmigen/hdl/xfrm.py
@@ -196,6 +196,10 @@ class StatementVisitor(metaclass=ABCMeta):
     def on_Assume(self, stmt):
         pass # :nocov:
 
+    @abstractmethod
+    def on_Cover(self, stmt):
+        pass # :nocov:
+
     @abstractmethod
     def on_Switch(self, stmt):
         pass # :nocov:
@@ -217,6 +221,8 @@ class StatementVisitor(metaclass=ABCMeta):
             new_stmt = self.on_Assert(stmt)
         elif type(stmt) is Assume:
             new_stmt = self.on_Assume(stmt)
+        elif type(stmt) is Cover:
+            new_stmt = self.on_Cover(stmt)
         elif isinstance(stmt, Switch):
             # Uses `isinstance()` and not `type() is` because nmigen.compat requires it.
             new_stmt = self.on_Switch(stmt)
@@ -247,6 +253,9 @@ class StatementTransformer(StatementVisitor):
     def on_Assume(self, stmt):
         return Assume(self.on_value(stmt.test), _check=stmt._check, _en=stmt._en)
 
+    def on_Cover(self, stmt):
+        return Cover(self.on_value(stmt.test), _check=stmt._check, _en=stmt._en)
+
     def on_Switch(self, stmt):
         cases = OrderedDict((k, self.on_statement(s)) for k, s in stmt.cases.items())
         return Switch(self.on_value(stmt.test), cases)
@@ -396,11 +405,12 @@ class DomainCollector(ValueVisitor, StatementVisitor):
         self.on_value(stmt.lhs)
         self.on_value(stmt.rhs)
 
-    def on_Assert(self, stmt):
+    def on_property(self, stmt):
         self.on_value(stmt.test)
 
-    def on_Assume(self, stmt):
-        self.on_value(stmt.test)
+    on_Assert = on_property
+    on_Assume = on_property
+    on_Cover  = on_property
 
     def on_Switch(self, stmt):
         self.on_value(stmt.test)
@@ -598,12 +608,13 @@ class SampleLowerer(FragmentTransformer, ValueTransformer, StatementTransformer)
 
 
 class SwitchCleaner(StatementVisitor):
-    def on_Assign(self, stmt):
+    def on_ignore(self, stmt):
         return stmt
 
-    on_Assert = on_Assign
-
-    on_Assume = on_Assign
+    on_Assign = on_ignore
+    on_Assert = on_ignore
+    on_Assume = on_ignore
+    on_Cover  = on_ignore
 
     def on_Switch(self, stmt):
         cases = OrderedDict((k, self.on_statement(s)) for k, s in stmt.cases.items())
@@ -651,9 +662,14 @@ class LHSGroupAnalyzer(StatementVisitor):
         if lhs_signals:
             self.unify(*stmt._lhs_signals())
 
-    on_Assert = on_Assign
+    def on_property(self, stmt):
+        lhs_signals = stmt._lhs_signals()
+        if lhs_signals:
+            self.unify(*stmt._lhs_signals())
 
-    on_Assume = on_Assign
+    on_Assert = on_property
+    on_Assume = on_property
+    on_Cover  = on_property
 
     def on_Switch(self, stmt):
         for case_stmts in stmt.cases.values():
@@ -681,12 +697,14 @@ class LHSGroupFilter(SwitchCleaner):
             if any_lhs_signal in self.signals:
                 return stmt
 
-    def on_Assert(self, stmt):
+    def on_property(self, stmt):
         any_lhs_signal = next(iter(stmt._lhs_signals()))
         if any_lhs_signal in self.signals:
             return stmt
 
-    on_Assume = on_Assert
+    on_Assert = on_property
+    on_Assume = on_property
+    on_Cover  = on_property
 
 
 class _ControlInserter(FragmentTransformer):