1 """ key strategic example showing how to do multi-input fan-in into a
2 multi-stage pipeline, then multi-output fanout.
4 the multiplex ID from the fan-in is passed in to the pipeline, preserved,
5 and used as a routing ID on the fanout.
8 from random
import randint
10 from nmigen
import Module
, Signal
, Cat
, Value
, Elaboratable
11 from nmigen
.compat
.sim
import run_simulation
12 from nmigen
.cli
import verilog
, rtlil
14 from nmutil
.multipipe
import CombMultiOutPipeline
, CombMuxOutPipe
15 from nmutil
.multipipe
import PriorityCombMuxInPipe
16 from nmutil
.singlepipe
import SimpleHandshake
, RecordObject
, Object
19 class PassData2(RecordObject
):
21 RecordObject
.__init
__(self
)
22 self
.muxid
= Signal(2, reset_less
=True)
23 self
.idx
= Signal(8, reset_less
=True)
24 self
.data
= Signal(16, reset_less
=True)
27 class PassData(Object
):
30 self
.muxid
= Signal(2, reset_less
=True)
31 self
.idx
= Signal(8, reset_less
=True)
32 self
.data
= Signal(16, reset_less
=True)
36 class PassThroughStage
:
40 return self
.ispec() # same as ospec
43 return i
# pass-through
47 class PassThroughPipe(SimpleHandshake
):
49 SimpleHandshake
.__init
__(self
, PassThroughStage())
53 def __init__(self
, dut
):
58 for muxid
in range(dut
.num_rows
):
61 for i
in range(self
.tlen
):
62 self
.di
[muxid
][i
] = randint(0, 255) + (muxid
<<8)
63 self
.do
[muxid
][i
] = self
.di
[muxid
][i
]
65 def send(self
, muxid
):
66 for i
in range(self
.tlen
):
67 op2
= self
.di
[muxid
][i
]
68 rs
= self
.dut
.p
[muxid
]
69 yield rs
.i_valid
.eq(1)
70 yield rs
.i_data
.data
.eq(op2
)
71 yield rs
.i_data
.idx
.eq(i
)
72 yield rs
.i_data
.muxid
.eq(muxid
)
74 o_p_ready
= yield rs
.o_ready
77 o_p_ready
= yield rs
.o_ready
79 print ("send", muxid
, i
, hex(op2
))
81 yield rs
.i_valid
.eq(0)
82 # wait random period of time before queueing another value
83 for i
in range(randint(0, 3)):
86 yield rs
.i_valid
.eq(0)
89 print ("send ended", muxid
)
91 ## wait random period of time before queueing another value
92 #for i in range(randint(0, 3)):
95 #send_range = randint(0, 3)
99 # send = randint(0, send_range) != 0
101 def rcv(self
, muxid
):
103 #stall_range = randint(0, 3)
104 #for j in range(randint(1,10)):
105 # stall = randint(0, stall_range) != 0
106 # yield self.dut.n[0].i_ready.eq(stall)
108 n
= self
.dut
.n
[muxid
]
109 yield n
.i_ready
.eq(1)
111 o_n_valid
= yield n
.o_valid
112 i_n_ready
= yield n
.i_ready
113 if not o_n_valid
or not i_n_ready
:
116 out_muxid
= yield n
.o_data
.muxid
117 out_i
= yield n
.o_data
.idx
118 out_v
= yield n
.o_data
.data
120 print ("recv", out_muxid
, out_i
, hex(out_v
))
122 # see if this output has occurred already, delete it if it has
123 assert muxid
== out_muxid
, \
124 "out_muxid %d not correct %d" % (out_muxid
, muxid
)
125 assert out_i
in self
.do
[muxid
], "out_i %d not in array %s" % \
126 (out_i
, repr(self
.do
[muxid
]))
127 assert self
.do
[muxid
][out_i
] == out_v
# pass-through data
128 del self
.do
[muxid
][out_i
]
130 # check if there's any more outputs
131 if len(self
.do
[muxid
]) == 0:
133 print ("recv ended", muxid
)
136 class TestPriorityMuxPipe(PriorityCombMuxInPipe
):
137 def __init__(self
, num_rows
):
138 self
.num_rows
= num_rows
139 stage
= PassThroughStage()
140 PriorityCombMuxInPipe
.__init
__(self
, stage
, p_len
=self
.num_rows
)
144 def __init__(self
, dut
):
149 for i
in range(self
.tlen
* dut
.num_rows
):
153 muxid
= randint(0, dut
.num_rows
-1)
154 data
= randint(0, 255) + (muxid
<<8)
157 for i
in range(self
.tlen
* dut
.num_rows
):
159 muxid
= self
.di
[i
][1]
161 yield rs
.i_valid
.eq(1)
162 yield rs
.i_data
.data
.eq(op2
)
163 yield rs
.i_data
.muxid
.eq(muxid
)
165 o_p_ready
= yield rs
.o_ready
168 o_p_ready
= yield rs
.o_ready
170 print ("send", muxid
, i
, hex(op2
))
172 yield rs
.i_valid
.eq(0)
173 # wait random period of time before queueing another value
174 for i
in range(randint(0, 3)):
177 yield rs
.i_valid
.eq(0)
180 class TestMuxOutPipe(CombMuxOutPipe
):
181 def __init__(self
, num_rows
):
182 self
.num_rows
= num_rows
183 stage
= PassThroughStage()
184 CombMuxOutPipe
.__init
__(self
, stage
, n_len
=self
.num_rows
)
187 class TestInOutPipe(Elaboratable
):
188 def __init__(self
, num_rows
=4):
189 self
.num_rows
= num_rows
190 self
.inpipe
= TestPriorityMuxPipe(num_rows
) # fan-in (combinatorial)
191 self
.pipe1
= PassThroughPipe() # stage 1 (clock-sync)
192 self
.pipe2
= PassThroughPipe() # stage 2 (clock-sync)
193 self
.outpipe
= TestMuxOutPipe(num_rows
) # fan-out (combinatorial)
195 self
.p
= self
.inpipe
.p
# kinda annoying,
196 self
.n
= self
.outpipe
.n
# use pipe in/out as this class in/out
197 self
._ports
= self
.inpipe
.ports() + self
.outpipe
.ports()
199 def elaborate(self
, platform
):
201 m
.submodules
.inpipe
= self
.inpipe
202 m
.submodules
.pipe1
= self
.pipe1
203 m
.submodules
.pipe2
= self
.pipe2
204 m
.submodules
.outpipe
= self
.outpipe
206 m
.d
.comb
+= self
.inpipe
.n
.connect_to_next(self
.pipe1
.p
)
207 m
.d
.comb
+= self
.pipe1
.connect_to_next(self
.pipe2
)
208 m
.d
.comb
+= self
.pipe2
.connect_to_next(self
.outpipe
)
217 dut
= TestInOutPipe()
218 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
219 with
open("test_inoutmux_pipe.il", "w") as f
:
221 #run_simulation(dut, testbench(dut), vcd_name="test_inputgroup.vcd")
223 test
= InputTest(dut
)
224 run_simulation(dut
, [test
.rcv(1), test
.rcv(0),
225 test
.rcv(3), test
.rcv(2),
226 test
.send(0), test
.send(1),
227 test
.send(3), test
.send(2),
229 vcd_name
="test_inoutmux_pipe.vcd")
231 if __name__
== '__main__':