src/nmutil/test/test_lut.py

   1 # SPDX-License-Identifier: LGPL-3-or-later
   2 # Copyright 2021 Jacob Lifshay
   3
   4 # Funded by NLnet Assure Programme 2021-02-052, https://nlnet.nl/assure part
   5 # of Horizon 2020 EU Programme 957073.
   6
   7 import unittest
   8 from nmigen.hdl.ast import AnyConst, Assert, Signal
   9 from nmigen.hdl.dsl import Module
  10 from nmutil.formaltest import FHDLTestCase
  11 from nmutil.lut import BitwiseMux, BitwiseLut, TreeBitwiseLut
  12 from nmigen.sim import Delay
  13 from nmutil.sim_util import do_sim, hash_256
  14
  15
  16 class TestBitwiseMux(FHDLTestCase):
  17     def test(self):
  18         width = 2
  19         dut = BitwiseMux(width)
  20
  21         def case(sel, t, f, expected):
  22             with self.subTest(sel=bin(sel), t=bin(t), f=bin(f)):
  23                 yield dut.sel.eq(sel)
  24                 yield dut.t.eq(t)
  25                 yield dut.f.eq(f)
  26                 yield Delay(1e-6)
  27                 output = yield dut.output
  28                 with self.subTest(output=bin(output), expected=bin(expected)):
  29                     self.assertEqual(expected, output)
  30
  31         def process():
  32             for sel in range(2 ** width):
  33                 for t in range(2 ** width):
  34                     for f in range(2**width):
  35                         expected = 0
  36                         for i in range(width):
  37                             if sel & 2 ** i:
  38                                 if t & 2 ** i:
  39                                     expected |= 2 ** i
  40                             elif f & 2 ** i:
  41                                 expected |= 2 ** i
  42                         yield from case(sel, t, f, expected)
  43         with do_sim(self, dut, [dut.sel, dut.t, dut.f, dut.output]) as sim:
  44             sim.add_process(process)
  45             sim.run()
  46
  47     def test_formal(self):
  48         width = 2
  49         dut = BitwiseMux(width)
  50         m = Module()
  51         m.submodules.dut = dut
  52         m.d.comb += dut.sel.eq(AnyConst(width))
  53         m.d.comb += dut.f.eq(AnyConst(width))
  54         m.d.comb += dut.t.eq(AnyConst(width))
  55         for i in range(width):
  56             with m.If(dut.sel[i]):
  57                 m.d.comb += Assert(dut.t[i] == dut.output[i])
  58             with m.Else():
  59                 m.d.comb += Assert(dut.f[i] == dut.output[i])
  60         self.assertFormal(m)
  61
  62
  63 class TestBitwiseLut(FHDLTestCase):
  64     def tst(self, cls):
  65         dut = cls(3, 16)
  66         mask = 2 ** dut.width - 1
  67         lut_mask = 2 ** dut.lut.width - 1
  68
  69         def case(in0, in1, in2, lut):
  70             expected = 0
  71             for i in range(dut.width):
  72                 lut_index = 0
  73                 if in0 & 2 ** i:
  74                     lut_index |= 2 ** 0
  75                 if in1 & 2 ** i:
  76                     lut_index |= 2 ** 1
  77                 if in2 & 2 ** i:
  78                     lut_index |= 2 ** 2
  79                 if lut & 2 ** lut_index:
  80                     expected |= 2 ** i
  81             with self.subTest(in0=bin(in0), in1=bin(in1), in2=bin(in2),
  82                               lut=bin(lut)):
  83                 yield dut.inputs[0].eq(in0)
  84                 yield dut.inputs[1].eq(in1)
  85                 yield dut.inputs[2].eq(in2)
  86                 yield dut.lut.eq(lut)
  87                 yield Delay(1e-6)
  88                 output = yield dut.output
  89                 with self.subTest(output=bin(output), expected=bin(expected)):
  90                     self.assertEqual(expected, output)
  91
  92         def process():
  93             for shift in range(dut.lut.width):
  94                 with self.subTest(shift=shift):
  95                     yield from case(in0=0xAAAA, in1=0xCCCC, in2=0xF0F0,
  96                                     lut=1 << shift)
  97             for case_index in range(100):
  98                 with self.subTest(case_index=case_index):
  99                     in0 = hash_256(f"{case_index} in0") & mask
 100                     in1 = hash_256(f"{case_index} in1") & mask
 101                     in2 = hash_256(f"{case_index} in2") & mask
 102                     lut = hash_256(f"{case_index} lut") & lut_mask
 103                     yield from case(in0, in1, in2, lut)
 104         with do_sim(self, dut, [*dut.inputs, dut.lut, dut.output]) as sim:
 105             sim.add_process(process)
 106             sim.run()
 107
 108     def tst_formal(self, cls):
 109         dut = cls(3, 16)
 110         m = Module()
 111         m.submodules.dut = dut
 112         m.d.comb += dut.inputs[0].eq(AnyConst(dut.width))
 113         m.d.comb += dut.inputs[1].eq(AnyConst(dut.width))
 114         m.d.comb += dut.inputs[2].eq(AnyConst(dut.width))
 115         m.d.comb += dut.lut.eq(AnyConst(dut.lut.width))
 116         for i in range(dut.width):
 117             lut_index = Signal(dut.input_count, name=f"lut_index_{i}")
 118             for j in range(dut.input_count):
 119                 m.d.comb += lut_index[j].eq(dut.inputs[j][i])
 120             for j in range(dut.lut.width):
 121                 with m.If(lut_index == j):
 122                     m.d.comb += Assert(dut.lut[j] == dut.output[i])
 123         self.assertFormal(m)
 124
 125     def test(self):
 126         self.tst(BitwiseLut)
 127
 128     def test_tree(self):
 129         self.tst(TreeBitwiseLut)
 130
 131     def test_formal(self):
 132         self.tst_formal(BitwiseLut)
 133
 134     def test_tree_formal(self):
 135         self.tst_formal(TreeBitwiseLut)
 136
 137
 138 if __name__ == "__main__":
 139     unittest.main()