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(parent: c63d1f2) | patch
more code-comments on BitwiseLut
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 17 Dec 2021 12:24:07 +0000 (12:24 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 17 Dec 2021 12:24:07 +0000 (12:24 +0000)
commit32dbf7ea5194f9f4593f72629fc9a28a8f9d5cc5
tree67cf0d5c354356dd397044c4c3005026356e8753tree
parentc63d1f2b483573fae75af6688c07409b84efa7e4commit | diff
more code-comments on BitwiseLut
also minor rewrite/style to avoid yosys creating large copies
of expressions (store in temporary signals).
the temp signals have the advantage of drastically simplifying and
clarifying the yosys graphviz output, making it easier to visually
inspect the correctness of the HDL
src/nmutil/lut.py diff | blob | history