use unittest.TestCase rather than FHDLTestCase

diff --git a/src/nmutil/test/test_clz.py b/src/nmutil/test/test_clz.py
index 1d066b43dec56c661f76df6d92243ef1f22440fc..09beb7311363e01e5750d5bf6e4216fc9266c85c 100644 (file)
--- a/src/nmutil/test/test_clz.py
+++ b/src/nmutil/test/test_clz.py
@@ -1,6 +1,5 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Simulator, Delay
-from nmigen.test.utils import FHDLTestCase
 
 from nmutil.clz import CLZ
 import unittest
@@ -8,7 +7,7 @@ import math
 import random
 
 
-class CLZTestCase(FHDLTestCase):
+class CLZTestCase(unittest.TestCase):
     def run_test(self, inputs, width=8):
 
         m = Module()