nmutil.git
7 days agopin some dependency versions master
Jacob Lifshay [Thu, 12 May 2022 01:14:57 +0000 (18:14 -0700)]
pin some dependency versions

8 days agostop possibility of infinite recursion in stages which
Luke Kenneth Casson Leighton [Wed, 11 May 2022 10:17:16 +0000 (11:17 +0100)]
stop possibility of infinite recursion in stages which
set "stage = self"

9 days agorename proof_clz.py -> test_clz.py so it's run by pytest
Jacob Lifshay [Tue, 10 May 2022 01:41:54 +0000 (18:41 -0700)]
rename proof_clz.py -> test_clz.py so it's run by pytest

9 days agofix .gitlab-ci.yml
Jacob Lifshay [Tue, 10 May 2022 01:40:17 +0000 (18:40 -0700)]
fix .gitlab-ci.yml

2 weeks agorewrite test_clz.py to actually test both CLZ and clz.
Jacob Lifshay [Thu, 5 May 2022 05:50:00 +0000 (22:50 -0700)]
rewrite test_clz.py to actually test both CLZ and clz.

it didn't actually test any simulation outputs of CLZ before.

2 weeks agoadd clz function
Jacob Lifshay [Thu, 5 May 2022 05:49:37 +0000 (22:49 -0700)]
add clz function

2 weeks agofix RippleMSB
Jacob Lifshay [Thu, 5 May 2022 04:24:08 +0000 (21:24 -0700)]
fix RippleMSB

TODO: add tests

https://bugs.libre-soc.org/show_bug.cgi?id=798#c5

3 weeks agoRevert "add reduce_only option to prefix_sum_ops"
Jacob Lifshay [Fri, 22 Apr 2022 22:01:09 +0000 (15:01 -0700)]
Revert "add reduce_only option to prefix_sum_ops"

it doesn't work when the element count isn't a power-of-2

This reverts commit c4357f7839c612a9c560a2bda14c34af6adee87b.

3 weeks agoadd reduce_only option to prefix_sum_ops
Jacob Lifshay [Fri, 22 Apr 2022 21:53:06 +0000 (14:53 -0700)]
add reduce_only option to prefix_sum_ops

3 weeks agoautoformat code
Jacob Lifshay [Fri, 22 Apr 2022 21:47:50 +0000 (14:47 -0700)]
autoformat code

5 weeks agowhitespace cleanup:
Luke Kenneth Casson Leighton [Sat, 9 Apr 2022 05:47:39 +0000 (06:47 +0100)]
whitespace cleanup:
* 80-char limit
* {code} {semi-colon} {docstring} reduces line-count, increases clarity
nothing can be done about URLs greater than 80 chars unfortunately

5 weeks agoadd prefix sum render tests
Jacob Lifshay [Sat, 9 Apr 2022 03:01:24 +0000 (20:01 -0700)]
add prefix sum render tests

5 weeks agoadd prefix_sum and initial tests
Jacob Lifshay [Sat, 9 Apr 2022 02:47:50 +0000 (19:47 -0700)]
add prefix_sum and initial tests

5 weeks agoadd SPDX-License-Identifier comments rather than using License:
Jacob Lifshay [Fri, 8 Apr 2022 23:26:58 +0000 (16:26 -0700)]
add SPDX-License-Identifier comments rather than using License:

5 weeks agoformat code
Jacob Lifshay [Fri, 8 Apr 2022 23:23:51 +0000 (16:23 -0700)]
format code

5 weeks agoformat and move comment block into fake docstring
Jacob Lifshay [Fri, 8 Apr 2022 23:15:41 +0000 (16:15 -0700)]
format and move comment block into fake docstring

otherwise autopep8 tries to move the comments to the top of the
file and smush the imports right against like()

6 weeks agoadd default argument fn=None to treereduce (identity operation)
Luke Kenneth Casson Leighton [Tue, 5 Apr 2022 14:38:14 +0000 (15:38 +0100)]
add default argument fn=None to treereduce (identity operation)
clean up docstring

6 weeks agocreate Ripple module, now joined by RippleMSB
Luke Kenneth Casson Leighton [Tue, 5 Apr 2022 10:30:10 +0000 (11:30 +0100)]
create Ripple module, now joined by RippleMSB

6 weeks agomove clmul files into nmigen-gf.git
Jacob Lifshay [Mon, 4 Apr 2022 05:42:27 +0000 (22:42 -0700)]
move clmul files into nmigen-gf.git

https://git.libre-soc.org/?p=nmigen-gf.git;a=commit;h=926798b6e232f09a36773be07de2d90e3fd431a4
src/nmutil/clmul.py => nmigen-gf.git/src/nmigen_gf/hdl/clmul.py
src/nmutil/test/test_clmul.py => nmigen-gf.git/src/nmigen_gf/hdl/test/test_clmul.py

7 weeks agofix accidentally wrong copyright year
Jacob Lifshay [Fri, 25 Mar 2022 03:26:43 +0000 (20:26 -0700)]
fix accidentally wrong copyright year

7 weeks agoadd CLMulAdd and tests
Jacob Lifshay [Wed, 23 Mar 2022 05:41:29 +0000 (22:41 -0700)]
add CLMulAdd and tests

2 months agoadd il generation by default
Jacob Lifshay [Tue, 1 Mar 2022 22:52:30 +0000 (14:52 -0800)]
add il generation by default

3 months agoFixed input shift reg signal name
Andrey Miroshnikov [Tue, 15 Feb 2022 11:35:59 +0000 (11:35 +0000)]
Fixed input shift reg signal name

3 months agoadd lut2 ilang output to lut.py to help testing
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 17:34:13 +0000 (17:34 +0000)]
add lut2 ilang output to lut.py to help testing

3 months agostore latch next in temporary
Luke Kenneth Casson Leighton [Mon, 31 Jan 2022 16:13:15 +0000 (16:13 +0000)]
store latch next in temporary

4 months agoremove unused import
Jacob Lifshay [Thu, 6 Jan 2022 02:14:39 +0000 (18:14 -0800)]
remove unused import

4 months agoPLRU interface signals (acc_i and acc_en) were reversed
Luke Kenneth Casson Leighton [Wed, 5 Jan 2022 14:23:13 +0000 (14:23 +0000)]
PLRU interface signals (acc_i and acc_en) were reversed
(no unit test exists for this module yet)

4 months agouse bit_length rather than log2_int function in mask.py
Luke Kenneth Casson Leighton [Wed, 5 Jan 2022 14:14:29 +0000 (14:14 +0000)]
use bit_length rather than log2_int function in mask.py

4 months agoredo grev
Jacob Lifshay [Thu, 23 Dec 2021 04:43:52 +0000 (20:43 -0800)]
redo grev

4 months agoremove redundant comments/docs
Jacob Lifshay [Thu, 23 Dec 2021 00:25:57 +0000 (16:25 -0800)]
remove redundant comments/docs

4 months agoadd additional command in comment
Jacob Lifshay [Wed, 22 Dec 2021 04:09:41 +0000 (20:09 -0800)]
add additional command in comment

4 months agorewrite TreeBitwiseLut to actually use a tree rather than a dict, hopefully making...
Jacob Lifshay [Wed, 22 Dec 2021 04:02:12 +0000 (20:02 -0800)]
rewrite TreeBitwiseLut to actually use a tree rather than a dict, hopefully making the code much easier to follow

4 months agomove writing rtlil into do_sim
Jacob Lifshay [Wed, 22 Dec 2021 03:57:15 +0000 (19:57 -0800)]
move writing rtlil into do_sim

4 months agoadd copyright notices
Jacob Lifshay [Wed, 22 Dec 2021 01:12:14 +0000 (17:12 -0800)]
add copyright notices

email and (C) aren't required according to https://www.gnu.org/licenses/gpl-howto.html

4 months agoremove unnecessary <no space here> messages
Jacob Lifshay [Wed, 22 Dec 2021 01:02:34 +0000 (17:02 -0800)]
remove unnecessary <no space here> messages

4 months agoformat code
Jacob Lifshay [Wed, 22 Dec 2021 00:58:24 +0000 (16:58 -0800)]
format code

5 months agoinput is a keyword in python
Luke Kenneth Casson Leighton [Fri, 17 Dec 2021 23:01:35 +0000 (23:01 +0000)]
input is a keyword in python

5 months agoinput is a keyword in python
Luke Kenneth Casson Leighton [Fri, 17 Dec 2021 22:55:19 +0000 (22:55 +0000)]
input is a keyword in python

5 months agocleanup chunk_size and list of steps in GRev
Luke Kenneth Casson Leighton [Fri, 17 Dec 2021 22:43:53 +0000 (22:43 +0000)]
cleanup chunk_size and list of steps in GRev

5 months agoadd NLnet Grant References
Luke Kenneth Casson Leighton [Fri, 17 Dec 2021 21:55:37 +0000 (21:55 +0000)]
add NLnet Grant References

5 months ago* moved the grev formal correctness assertions into the module
Luke Kenneth Casson Leighton [Fri, 17 Dec 2021 21:52:14 +0000 (21:52 +0000)]
* moved the grev formal correctness assertions into the module
  (under the protection of "if platform == formal")
* moved grev assert on internal variable (dut._steps) inside the
  unit test process() function so that it is after the elaborate()
  which is where ._steps gets created
  (this keeps Grev._steps a private variable for unit tests only)
* added TODO comment about the copyright notice at the top of test_grev.py

5 months agomore code-comments on BitwiseLut
Luke Kenneth Casson Leighton [Fri, 17 Dec 2021 12:24:07 +0000 (12:24 +0000)]
more code-comments on BitwiseLut
also minor rewrite/style to avoid yosys creating large copies
of expressions (store in temporary signals).
the temp signals have the advantage of drastically simplifying and
clarifying the yosys graphviz output, making it easier to visually
inspect the correctness of the HDL

5 months agorewrite GRev. put in code-comments and some more TODOs
Luke Kenneth Casson Leighton [Fri, 17 Dec 2021 12:22:27 +0000 (12:22 +0000)]
rewrite GRev. put in code-comments and some more TODOs

5 months agoclean up rest of grev.py docs
Jacob Lifshay [Fri, 17 Dec 2021 03:27:06 +0000 (19:27 -0800)]
clean up rest of grev.py docs

5 months agoclarify docs
Jacob Lifshay [Fri, 17 Dec 2021 03:23:26 +0000 (19:23 -0800)]
clarify docs

5 months agoclarify docstring
Jacob Lifshay [Fri, 17 Dec 2021 03:14:33 +0000 (19:14 -0800)]
clarify docstring

5 months agoadd grev test and formal proof
Jacob Lifshay [Fri, 17 Dec 2021 03:12:54 +0000 (19:12 -0800)]
add grev test and formal proof

5 months agoclean up grev
Jacob Lifshay [Fri, 17 Dec 2021 03:12:39 +0000 (19:12 -0800)]
clean up grev

5 months agomove do_sim and hash_256 to separate module
Jacob Lifshay [Fri, 17 Dec 2021 01:37:26 +0000 (17:37 -0800)]
move do_sim and hash_256 to separate module

5 months agoadd docs
Jacob Lifshay [Fri, 17 Dec 2021 01:21:32 +0000 (17:21 -0800)]
add docs

5 months agosimplify lut.py
Jacob Lifshay [Fri, 17 Dec 2021 01:20:50 +0000 (17:20 -0800)]
simplify lut.py

5 months agowhoops just step through i not list
Luke Kenneth Casson Leighton [Sun, 12 Dec 2021 14:35:07 +0000 (14:35 +0000)]
whoops just step through i not list

5 months agoremove the pre-added array, remove the sub-function (sub-functions
Luke Kenneth Casson Leighton [Sun, 12 Dec 2021 14:32:24 +0000 (14:32 +0000)]
remove the pre-added array, remove the sub-function (sub-functions
are a bit... naff), accumulate the list on-demand, provide comments
about what that list is for

5 months agomore comments
Luke Kenneth Casson Leighton [Sat, 11 Dec 2021 15:57:05 +0000 (15:57 +0000)]
more comments
reason: understanding lambda networks (aka butterfly aka generalised-rev)
is a bit of a pig

5 months agosome more hints/comments
Luke Kenneth Casson Leighton [Sat, 11 Dec 2021 15:37:35 +0000 (15:37 +0000)]
some more hints/comments

5 months agoadd some comments (locations for comments to be added)
Luke Kenneth Casson Leighton [Sat, 11 Dec 2021 15:29:09 +0000 (15:29 +0000)]
add some comments (locations for comments to be added)

5 months agoadd initial grev implementation
Jacob Lifshay [Fri, 10 Dec 2021 23:42:11 +0000 (15:42 -0800)]
add initial grev implementation

5 months agoremove unused import
Jacob Lifshay [Fri, 10 Dec 2021 23:30:44 +0000 (15:30 -0800)]
remove unused import

5 months agofix to nmutil workaround for detecting new Simulator API
Luke Kenneth Casson Leighton [Wed, 8 Dec 2021 12:48:11 +0000 (12:48 +0000)]
fix to nmutil workaround for detecting new Simulator API
the engine argument if already provided, just use that

5 months agoadd a PLRUs module which selects between multiple PLRUs
Luke Kenneth Casson Leighton [Mon, 6 Dec 2021 17:00:56 +0000 (17:00 +0000)]
add a PLRUs module which selects between multiple PLRUs

5 months agoadd nmigen/_toolchain/__init__ as toolchain.py to avoid depending on internal API
Jacob Lifshay [Thu, 2 Dec 2021 01:50:41 +0000 (17:50 -0800)]
add nmigen/_toolchain/__init__ as toolchain.py to avoid depending on internal API

5 months agoremove redundant overrides of stuff that's aready in unittest in python >=3.7
Jacob Lifshay [Thu, 2 Dec 2021 01:44:22 +0000 (17:44 -0800)]
remove redundant overrides of stuff that's aready in unittest in python >=3.7

5 months agoadd missing import Statement for assertRepr
Jacob Lifshay [Thu, 2 Dec 2021 01:39:40 +0000 (17:39 -0800)]
add missing import Statement for assertRepr

5 months agochange FHDLTestCase to use get_test_path
Jacob Lifshay [Thu, 2 Dec 2021 01:26:13 +0000 (17:26 -0800)]
change FHDLTestCase to use get_test_path

Fixes the issue with FHDLTestCase sometimes using the same directory for
different test cases, causing problems for running tests in parallel.

5 months agoswitch test_lut to use FHDLTestCase
Jacob Lifshay [Thu, 2 Dec 2021 01:24:18 +0000 (17:24 -0800)]
switch test_lut to use FHDLTestCase

5 months agoformat code
Jacob Lifshay [Thu, 2 Dec 2021 01:03:38 +0000 (17:03 -0800)]
format code

5 months agonote about not setting the muxid in ReservationStations2
Luke Kenneth Casson Leighton [Wed, 1 Dec 2021 13:27:38 +0000 (13:27 +0000)]
note about not setting the muxid in ReservationStations2

5 months agoupdate SRLatch API to include q_int
Luke Kenneth Casson Leighton [Sun, 28 Nov 2021 14:38:50 +0000 (14:38 +0000)]
update SRLatch API to include q_int

6 months agoadd Array-based version of BitwiseLut, renaming old version to TreeBitwiseLut in...
Jacob Lifshay [Wed, 17 Nov 2021 18:58:22 +0000 (10:58 -0800)]
add Array-based version of BitwiseLut, renaming old version to TreeBitwiseLut in case we need it

6 months agoadd formal tests for BitwiseLut
Jacob Lifshay [Wed, 17 Nov 2021 04:07:41 +0000 (20:07 -0800)]
add formal tests for BitwiseLut

6 months agoadd BitwiseLut and tests
Jacob Lifshay [Wed, 17 Nov 2021 03:08:35 +0000 (19:08 -0800)]
add BitwiseLut and tests

6 months agoreturn latchregister results so that it can be further set/modified
Luke Kenneth Casson Leighton [Mon, 8 Nov 2021 23:33:02 +0000 (23:33 +0000)]
return latchregister results so that it can be further set/modified

6 months agoallow name of ALU to be set in ReservationStations2
Luke Kenneth Casson Leighton [Sun, 7 Nov 2021 13:25:45 +0000 (13:25 +0000)]
allow name of ALU to be set in ReservationStations2

6 months agoreduce number of wait states in ReservationStations2 by detecting
Luke Kenneth Casson Leighton [Sun, 7 Nov 2021 13:14:05 +0000 (13:14 +0000)]
reduce number of wait states in ReservationStations2 by detecting
opportunities for sending (and receiving) data immediately.

the previous version was a 4-cycle FSM.  however it is perfectly
fine to detect, in the very first phase (as part of ACCEPTANCE),
if the ALU is already ready to accept.  effectively this combines
phase 1 and phase 2.  if the ALU was *not* ready then and only
then will a given FSM move to phase 2 (after buffering the data)

likewise, when data comes out of the ALU, there is an opportunity
to signal to the RS output that the data is in fact ready... *if*
the RS output was in fact waiting for it already.  again, this
combines phase 3 and phase 4.  again: if the RS output was not
ready, then a given FSM will move to phase 4 (again, after
buffering the data)

6 months agofixed bug in MultiCompUnit, can return to combinatorial setting
Luke Kenneth Casson Leighton [Sun, 7 Nov 2021 12:47:30 +0000 (12:47 +0000)]
fixed bug in MultiCompUnit, can return to combinatorial setting
https://bugs.libre-soc.org/show_bug.cgi?id=742

wrmask was interfering by being in too many places, and it is the
amalgamation of "data ok" signals.  wrmask had to be set and left
set, in order for (unnecessary) determination of end of the requests

6 months agobugfix new ReservationStations2
Luke Kenneth Casson Leighton [Thu, 4 Nov 2021 19:12:30 +0000 (19:12 +0000)]
bugfix new ReservationStations2
it is awful - horribly inefficient - but it "works"
lots of delays.  but, it passes i.e. does not blow up or cause hanging

6 months agoupdate ReservationStations2 to be a FSM. not a very efficient one, no
Luke Kenneth Casson Leighton [Thu, 4 Nov 2021 14:51:23 +0000 (14:51 +0000)]
update ReservationStations2 to be a FSM. not a very efficient one, no
combinatorial bypass at the moment.  takes 4 cycles to get any data through.
this can be reduced to 2, later

6 months agoadd start of new ReservationStations2 class
Luke Kenneth Casson Leighton [Wed, 3 Nov 2021 14:41:09 +0000 (14:41 +0000)]
add start of new ReservationStations2 class

6 months agoadd some debug output to Visitor2 (commented out)
Luke Kenneth Casson Leighton [Wed, 3 Nov 2021 14:40:07 +0000 (14:40 +0000)]
add some debug output to Visitor2 (commented out)

6 months agoadd name prefix to PrevControl and NextControl
Luke Kenneth Casson Leighton [Wed, 3 Nov 2021 14:39:04 +0000 (14:39 +0000)]
add name prefix to PrevControl and NextControl
(useful for multi-fan-in/out)

6 months agoReservationStations - or more to the point the CombMuxIn/MuxOut -
Luke Kenneth Casson Leighton [Mon, 1 Nov 2021 23:10:23 +0000 (23:10 +0000)]
ReservationStations - or more to the point the CombMuxIn/MuxOut -
are completely broken.  deep joy

6 months agomove call to self.process onto i_data in multipipe just like in singlepipe
Luke Kenneth Casson Leighton [Mon, 1 Nov 2021 21:46:22 +0000 (21:46 +0000)]
move call to self.process onto i_data in multipipe just like in singlepipe

6 months agoredo ReservationStations setup of pseudoalus
Luke Kenneth Casson Leighton [Mon, 1 Nov 2021 21:28:42 +0000 (21:28 +0000)]
redo ReservationStations setup of pseudoalus

6 months agoadd ALUProxy to ReservationStations class
Luke Kenneth Casson Leighton [Mon, 1 Nov 2021 20:15:34 +0000 (20:15 +0000)]
add ALUProxy to ReservationStations class

6 months agowhitspace
Luke Kenneth Casson Leighton [Wed, 6 Oct 2021 12:36:29 +0000 (13:36 +0100)]
whitspace

6 months agowhitespace
Luke Kenneth Casson Leighton [Wed, 6 Oct 2021 12:32:14 +0000 (13:32 +0100)]
whitespace

7 months agoadd deduped
Jacob Lifshay [Sat, 9 Oct 2021 01:00:10 +0000 (18:00 -0700)]
add deduped

7 months agomove type info into doc strings, since lkcl complains that he can't read type annotat...
Jacob Lifshay [Fri, 8 Oct 2021 23:43:03 +0000 (16:43 -0700)]
move type info into doc strings, since lkcl complains that he can't read type annotations.

Closes https://bugs.libre-soc.org/show_bug.cgi?id=721

7 months agoadd get_test_path function from simd_signal's util.py
Jacob Lifshay [Fri, 1 Oct 2021 22:13:08 +0000 (15:13 -0700)]
add get_test_path function from simd_signal's util.py

7 months agovarname error (extz_data not exts_data)
Luke Kenneth Casson Leighton [Thu, 30 Sep 2021 14:15:12 +0000 (15:15 +0100)]
varname error (extz_data not exts_data)

7 months agomorph exts/extz and add new "ext" function which takes shape arg
Luke Kenneth Casson Leighton [Wed, 29 Sep 2021 18:09:21 +0000 (19:09 +0100)]
morph exts/extz and add new "ext" function which takes shape arg

8 months agolikewise replace data_o with o_data and data_i with i_data
Luke Kenneth Casson Leighton [Tue, 24 Aug 2021 11:52:12 +0000 (12:52 +0100)]
likewise replace data_o with o_data and data_i with i_data

8 months agobig rename, global/search/replace of ready_o with o_ready and the other
Luke Kenneth Casson Leighton [Tue, 24 Aug 2021 10:21:57 +0000 (11:21 +0100)]
big rename, global/search/replace of ready_o with o_ready and the other
4 signals as well, valid_i -> i_valid
https://libera.irclog.whitequark.org/nmigen/2021-08-24#30728292;
to be consistent with nmigen standards

8 months agorename run_test to run_tst so nosetests3 skips it
Luke Kenneth Casson Leighton [Tue, 24 Aug 2021 10:14:24 +0000 (11:14 +0100)]
rename run_test to run_tst so nosetests3 skips it

11 months agoRemove comment sign and add correct path for nmigen intersphinx.
R Veera Kumar [Sat, 5 Jun 2021 01:59:55 +0000 (07:29 +0530)]
Remove comment sign and add correct path for nmigen intersphinx.

11 months agoAdd Makefile modified for sphinx
R Veera Kumar [Fri, 4 Jun 2021 20:08:12 +0000 (01:38 +0530)]
Add Makefile modified for sphinx

11 months agoInitial addition of sphinx documentation system.
R Veera Kumar [Fri, 4 Jun 2021 19:28:20 +0000 (00:58 +0530)]
Initial addition of sphinx documentation system.

Add run of sphinx-quickstart and manual modifications of files.

12 months agoupdate README
Luke Kenneth Casson Leighton [Tue, 4 May 2021 14:58:03 +0000 (15:58 +0100)]
update README

13 months agoadd OS Independent classifier
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 11:44:10 +0000 (12:44 +0100)]
add OS Independent classifier

13 months agoadd pypi upload to Makefile
Luke Kenneth Casson Leighton [Sun, 11 Apr 2021 23:57:51 +0000 (00:57 +0100)]
add pypi upload to Makefile