add ply and pygdbmi dependencies
[openpower-isa.git] / NEWS.txt
1 Release Notes Version 0.0.1 23 April 2021
2 -------------
3
4 The Libre-SOC Project is pleased to announce the first release of an
5 OpenPOWER ISA co-simulation test suite with its own built-in OpenPOWER
6 ISA Simulator.
7
8 https://git.libre-soc.org/?p=openpower-isa.git
9
10 Available also on pypi:
11 https://pypi.org/project/libresoc-openpower-isa/
12
13 Containing thousands of unit tests for OpenPOWER v3.0 its purpose is
14 to provide cross-emulator cross-simulator cross-HDL inter-verification,
15 and to enable and accelerate research and collaboration in OpenPOWER.
16
17 Currently included in co-simulation is:
18
19 * an internal OpenPOWER simulator written in python (ISACaller)
20 * a means to fire up qemu bare-metal programs using pygdbmi
21 * single-stepping followed by extraction of registers and memory
22 * comparison and reporting on any discrepancies
23
24 in this fashion, obscure previously undiscovered bugs in qemu have been
25 found and reported.
26
27 Libre-SOC's HDL (written in nmigen) also runs the exact same unit
28 tests, comparing through the same single-stepping, against ISACaller.
29 Having cross-verified ISACaller against qemu, running the same unit tests
30 against Libre-SOC HDL ensures that Libre-SOC's hardware implementation
31 behaves the same (minus the qemu bug).
32
33 https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/test/test_issuer.py;hb=HEAD
34
35 The project provides a useful bootstrap methodology for testing extensions
36 of the OpenPOWER ISA: currently, SVP64 (a Cray-style variable-length
37 Vector Extension to OpenPOWER) is currently being developed in the
38 simulator and in LibreSOC HDL.
39
40 Future plans are to add Microwatt and power-gem5 into the mix, as well
41 as ssh out to remote POWER9/10 compatible hardware, and also running
42 native gdb (obviously, only on actual OpenPOWER compatible hardware).
43 It would also be nice to receive patches adding IBM's proprietary
44 OpenPOWER emulator as well.
45
46 With power-gem5 having the exact same remote machine-driven gdb interface
47 as qemu, this one should be easy. Microwatt will require external access
48 via its DMI interface on a simulator of some kind (verilator, cocotb)
49 in order to read memory and registers.
50
51 The python-based simulator, ineptly named ISACaller, is noteworthy in
52 that not one single line of hand-generated python simulator code was
53 written, neither for the OpenPOWER ISA decoding nor for the emulated
54 execution of actual instructions.
55
56 Instead, information was extracted into human-readable machine-readable
57 CSV, text, and markdown files, and a compiler (language translator)
58 written. python-ply afficionados will love that the compiler was based
59 on GardenSnake.py
60
61 With the pseudocode and ISA Opcode fields having been extracted from the
62 OpenPOWER v3.0B ISA Manual, this means that the *actual specification
63 itself* (having been compiled to python) is what was tested by the
64 several thousand unit tests.
65
66 This gets particularly interesting when researching new extensions
67 to OpenPOWER, because the very first thing required is to add the
68 opcodes, fields, forms and pseudocode, for ISACaller to be able to
69 use it. This should make adding a proposed extension to the actual ISA
70 considerably smoother.
71
72 With the v3.0B pseusocode now proven as executable, there is no reason
73 why in future additional compilers (c, c++) or Formal Correctness Proofs
74 should not be at least partly auto-generated. More details here, in
75 the walkthrough:
76
77 https://libre-soc.org/3d_gpu/architecture/decoder/
78
79 Also potentially of huge value would be the addition of openocd support
80 via JTAG / DMI for OpenPOWER, then using JTAG it would be possible
81 not only to run the exact same unit tests against FPGAs and ASICSs, it
82 would be possible to run the same unit tests through litex "jtagremote",
83 and against cocotb as well. Hints on that, here:
84
85 https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/firmware_upload.py;h=05fe4879470c3fd3373f2ed68be21f740b46367d;hb=964a6afdf08fd924b75603b2d7bd3a31b9815561#l63
86
87 https://git.libre-soc.org/?p=libresoc-litex.git;a=blob;f=sim.py;h=8cddb39c6d2a5509bde635e2987055264c423b84;hb=1d20454df8ccfb8ccdd8b32d7138f38553c23f1d#l480
88
89 Note that the firmware_upload.py program speaks the exact same jtagremote
90 bitbanging protocol that is in upstream litex (and openocd). A patch
91 is available to litex which enables it for litex sim:
92
93 https://ftp.libre-soc.org/litex-sim-jtagremote.patch
94
95 Libre-SOC therefore cordially invites other parties interested
96 in OpenPOWER to collaborate in this weird and wonderful
97 cross-hardware-software project, which throws FPGAs, simulators,
98 emulators, language translators and hardware into a melting pot and
99 lights the blue touchpaper.
100
101 Questions and contributions welcomed at the libre-soc-dev mailing list,
102 and at #libre-soc on freenode.
103
104 This work is sponsored by NLnet under its Privacy and Enhanced Trust
105 Programme. http://nlnet.nl
106