221b8ad41b89391c5df1fb53a0d2cd4416389d17
[openpower-isa.git] / openpower / isa / av.mdwn
1 <!-- DRAFT Instructions for PowerISA Version 3.0 B Book 1 -->
2 <!-- https://libre-soc.org/openpower/sv/bitmanip/ -->
3 <!-- https://libre-soc.org/openpower/sv/av_opcodes/ -->
4
5 # DRAFT Minimum/Maximum (Rc=1)
6
7 MM-Form
8
9 * minmax. RT,RA,RB,MMM (Rc=1)
10
11 Pseudo-code:
12
13 a <- (RA|0)
14 b <- (RB)
15 if MMM[0] then # word mode
16 # shift left by XLEN/2 to make the dword comparison
17 # do word comparison of the original inputs
18 a <- a[XLEN/2:XLEN-1] || [0] * XLEN/2
19 b <- b[XLEN/2:XLEN-1] || [0] * XLEN/2
20 if MMM[1] then # signed mode
21 # invert sign bits to make the unsigned comparison
22 # do signed comparison of the original inputs
23 a[0] <- ¬a[0]
24 b[0] <- ¬b[0]
25 # if Rc = 1 then store the result of comparing a and b to CR0
26 if Rc = 1 then
27 if a <u b then
28 CR0 <- 0b100 || XER[SO]
29 if a = b then
30 CR0 <- 0b001 || XER[SO]
31 if a >u b then
32 CR0 <- 0b010 || XER[SO]
33 if MMM[2] then # max mode
34 # swap a and b to make the less than comparison do
35 # greater than comparison of the original inputs
36 t <- a
37 a <- b
38 b <- t
39 # store the entire selected source (even in word mode)
40 # if Rc = 1 then store the result of comparing a and b to CR0
41 if a <u b then RT <- (RA|0)
42 else RT <- (RB)
43
44 Special Registers Altered:
45
46 CR0 (if Rc=1)
47
48 # DRAFT Minimum/Maximum
49
50 MM-Form
51
52 * minmax RT,RA,RB,MMM (Rc=0)
53
54 Pseudo-code:
55
56 a <- (RA|0)
57 b <- (RB)
58 if MMM[0] then # word mode
59 # shift left by XLEN/2 to make the dword comparison
60 # do word comparison of the original inputs
61 a <- a[XLEN/2:XLEN-1] || [0] * XLEN/2
62 b <- b[XLEN/2:XLEN-1] || [0] * XLEN/2
63 if MMM[1] then # signed mode
64 # invert sign bits to make the unsigned comparison
65 # do signed comparison of the original inputs
66 a[0] <- ¬a[0]
67 b[0] <- ¬b[0]
68 # if Rc = 1 then store the result of comparing a and b to CR0
69 # if Rc = 1 then
70 # if a <u b then
71 # CR0 <- 0b100 || XER[SO]
72 # if a = b then
73 # CR0 <- 0b001 || XER[SO]
74 # if a >u b then
75 # CR0 <- 0b010 || XER[SO]
76 if MMM[2] then # max mode
77 # swap a and b to make the less than comparison do
78 # greater than comparison of the original inputs
79 t <- a
80 a <- b
81 b <- t
82 # store the entire selected source (even in word mode)
83 if a <u b then RT <- (RA|0)
84 else RT <- (RB)
85
86 Special Registers Altered:
87
88 None
89
90 # DRAFT Average Add
91
92 X-Form
93
94 * avgadd RT,RA,RB (Rc=0)
95 * avgadd. RT,RA,RB (Rc=1)
96
97 Pseudo-code:
98
99 a <- [0] * (XLEN+1)
100 b <- [0] * (XLEN+1)
101 a[1:XLEN] <- (RA)
102 b[1:XLEN] <- (RB)
103 r <- (a + b + 1)
104 RT <- r[0:XLEN-1]
105
106 Special Registers Altered:
107
108 CR0 (if Rc=1)
109
110 # DRAFT Absolute Signed Difference
111
112 X-Form
113
114 * absds RT,RA,RB (Rc=0)
115 * absds. RT,RA,RB (Rc=1)
116
117 Pseudo-code:
118
119 if (RA) < (RB) then RT <- ¬(RA) + (RB) + 1
120 else RT <- ¬(RB) + (RA) + 1
121
122 Special Registers Altered:
123
124 CR0 (if Rc=1)
125
126 # DRAFT Absolute Unsigned Difference
127
128 X-Form
129
130 * absdu RT,RA,RB (Rc=0)
131 * absdu. RT,RA,RB (Rc=1)
132
133 Pseudo-code:
134
135 if (RA) <u (RB) then RT <- ¬(RA) + (RB) + 1
136 else RT <- ¬(RB) + (RA) + 1
137
138 Special Registers Altered:
139
140 CR0 (if Rc=1)
141
142 # DRAFT Absolute Accumulate Unsigned Difference
143
144 X-Form
145
146 * absdacu RT,RA,RB (Rc=0)
147 * absdacu. RT,RA,RB (Rc=1)
148
149 Pseudo-code:
150
151 if (RA) <u (RB) then r <- ¬(RA) + (RB) + 1
152 else r <- ¬(RB) + (RA) + 1
153 RT <- (RT) + r
154
155 Special Registers Altered:
156
157 CR0 (if Rc=1)
158
159 # DRAFT Absolute Accumulate Signed Difference
160
161 X-Form
162
163 * absdacs RT,RA,RB (Rc=0)
164 * absdacs. RT,RA,RB (Rc=1)
165
166 Pseudo-code:
167
168 if (RA) < (RB) then r <- ¬(RA) + (RB) + 1
169 else r <- ¬(RB) + (RA) + 1
170 RT <- (RT) + r
171
172 Special Registers Altered:
173
174 CR0 (if Rc=1)
175
176 # Carry Propagate
177
178 X-Form
179
180 * cprop RT,RA,RB (Rc=0)
181 * cprop. RT,RA,RB (Rc=1)
182
183 Pseudo-code:
184
185 P <- (RA)
186 G <- (RB)
187 temp <- (P|G)+G
188 RT <- temp^P
189
190 Special Registers Altered:
191
192 CR0 (if Rc=1)
193
194 # DRAFT Bitmanip Masked
195
196 BM2-Form
197
198 * bmask RT,RA,RB,bm,L
199
200 Pseudo-code:
201
202 if _RB = 0 then mask <- [1] * XLEN
203 else mask <- (RB)
204 ra <- (RA) & mask
205 a1 <- ra
206 if bm[4] = 0 then a1 <- ¬ra
207 mode2 <- bm[2:3]
208 if mode2 = 0 then a2 <- (¬ra)+1
209 if mode2 = 1 then a2 <- ra-1
210 if mode2 = 2 then a2 <- ra+1
211 if mode2 = 3 then a2 <- ¬(ra+1)
212 a1 <- a1 & mask
213 a2 <- a2 & mask
214 # select operator
215 mode3 <- bm[0:1]
216 if mode3 = 0 then result <- a1 | a2
217 if mode3 = 1 then result <- a1 & a2
218 if mode3 = 2 then result <- a1 ^ a2
219 if mode3 = 3 then result <- undefined([0]*XLEN)
220 result <- result & mask
221 # optionally restore masked-out bits
222 if L = 1 then
223 result <- result | (RA & ¬mask)
224 RT <- result
225
226 Special Registers Altered:
227
228 None
229
230 # Load Floating-Point Immediate
231
232 DX-Form
233
234 * fmvis FRS,D
235
236 Pseudo-code:
237
238 bf16 <- d0 || d1 || d2
239 fp32 <- bf16 || [0]*16
240 FRS <- DOUBLE(fp32)
241
242 Special Registers Altered:
243
244 None
245
246 # Float Replace Lower-Half Single, Immediate
247
248 DX-Form
249
250 * fishmv FRS,D
251
252 Pseudo-code:
253
254 fp32 <- SINGLE((FRS))
255 fp32[16:31] <- d0 || d1 || d2
256 FRS <- DOUBLE(fp32)
257
258 Special Registers Altered:
259
260 None