1 <!-- X Instructions here described in PowerISA Version 3.0 B Book 1 -->
3 <!-- Section 3.3.9 Fixed-point arithmetic instructions. Pages 67 - 83 -->
13 RT <- (RA|0) + EXTS(SI)
15 Special Registers Altered:
19 # Add Immediate Shifted
27 RT <- (RA|0) + EXTS(SI || [0]*16)
29 Special Registers Altered:
33 # Add PC Immediate Shifted
42 RT <- NIA + EXTS(D || [0]*16)
44 Special Registers Altered:
52 * add RT,RA,RB (OE=0 Rc=0)
53 * add. RT,RA,RB (OE=0 Rc=1)
54 * addo RT,RA,RB (OE=1 Rc=0)
55 * addo. RT,RA,RB (OE=1 Rc=1)
61 Special Registers Altered:
70 * subf RT,RA,RB (OE=0 Rc=0)
71 * subf. RT,RA,RB (OE=0 Rc=1)
72 * subfo RT,RA,RB (OE=1 Rc=0)
73 * subfo. RT,RA,RB (OE=1 Rc=1)
77 RT <- ¬(RA) + (RB) + 1
79 Special Registers Altered:
84 # Add Immediate Carrying
94 Special Registers Altered:
98 # Add Immediate Carrying and Record
106 RT <- (RA) + EXTS(SI)
108 Special Registers Altered:
112 # Subtract From Immediate Carrying
120 RT <- ¬(RA) + EXTS(SI) + 1
122 Special Registers Altered:
130 * addc RT,RA,RB (OE=0 Rc=0)
131 * addc. RT,RA,RB (OE=0 Rc=1)
132 * addco RT,RA,RB (OE=1 Rc=0)
133 * addco. RT,RA,RB (OE=1 Rc=1)
139 Special Registers Altered:
145 # Subtract From Carrying
149 * subfc RT,RA,RB (OE=0 Rc=0)
150 * subfc. RT,RA,RB (OE=0 Rc=1)
151 * subfco RT,RA,RB (OE=1 Rc=0)
152 * subfco. RT,RA,RB (OE=1 Rc=1)
156 RT <- ¬(RA) + (RB) + 1
158 Special Registers Altered:
168 * adde RT,RA,RB (OE=0 Rc=0)
169 * adde. RT,RA,RB (OE=0 Rc=1)
170 * addeo RT,RA,RB (OE=1 Rc=0)
171 * addeo. RT,RA,RB (OE=1 Rc=1)
175 RT <- (RA) + (RB) + CA
177 Special Registers Altered:
183 # Subtract From Extended
187 * subfe RT,RA,RB (OE=0 Rc=0)
188 * subfe. RT,RA,RB (OE=0 Rc=1)
189 * subfeo RT,RA,RB (OE=1 Rc=0)
190 * subfeo. RT,RA,RB (OE=1 Rc=1)
194 RT <- ¬(RA) + (RB) + CA
196 Special Registers Altered:
202 # Add to Minus One Extended
206 * addme RT,RA (OE=0 Rc=0)
207 * addme. RT,RA (OE=0 Rc=1)
208 * addmeo RT,RA (OE=1 Rc=0)
209 * addmeo. RT,RA (OE=1 Rc=1)
215 Special Registers Altered:
221 # Subtract From Minus One Extended
225 * subfme RT,RA (OE=0 Rc=0)
226 * subfme. RT,RA (OE=0 Rc=1)
227 * subfmeo RT,RA (OE=1 Rc=0)
228 * subfmeo. RT,RA (OE=1 Rc=1)
234 Special Registers Altered:
240 # Add Extended using alternate carry bit
248 if CY=0 then RT <- (RA) + (RB) + OV
250 Special Registers Altered:
254 # Subtract From Zero Extended
258 * subfze RT,RA (OE=0 Rc=0)
259 * subfze. RT,RA (OE=0 Rc=1)
260 * subfzeo RT,RA (OE=1 Rc=0)
261 * subfzeo. RT,RA (OE=1 Rc=1)
267 Special Registers Altered:
273 # Add to Zero Extended
277 * addze RT,RA (OE=0 Rc=0)
278 * addze. RT,RA (OE=0 Rc=1)
279 * addzeo RT,RA (OE=1 Rc=0)
280 * addzeo. RT,RA (OE=1 Rc=1)
286 Special Registers Altered:
296 * neg RT,RA (OE=0 Rc=0)
297 * neg. RT,RA (OE=0 Rc=1)
298 * nego RT,RA (OE=1 Rc=0)
299 * nego. RT,RA (OE=1 Rc=1)
305 Special Registers Altered:
310 # Multiply Low Immediate
318 prod[0:(XLEN*2)-1] <- MULS((RA), EXTS(SI))
319 RT <- prod[XLEN:(XLEN*2)-1]
321 Special Registers Altered:
329 * mulhw RT,RA,RB (Rc=0)
330 * mulhw. RT,RA,RB (Rc=1)
334 prod[0:XLEN-1] <- MULS((RA)[XLEN/2:XLEN-1], (RB)[XLEN/2:XLEN-1])
335 RT[XLEN/2:XLEN-1] <- prod[0:(XLEN/2)-1]
336 RT[0:(XLEN/2)-1] <- undefined(prod[0:(XLEN/2)-1])
338 Special Registers Altered:
340 CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
346 * mullw RT,RA,RB (OE=0 Rc=0)
347 * mullw. RT,RA,RB (OE=0 Rc=1)
348 * mullwo RT,RA,RB (OE=1 Rc=0)
349 * mullwo. RT,RA,RB (OE=1 Rc=1)
353 prod[0:XLEN-1] <- MULS((RA)[XLEN/2:XLEN-1], (RB)[XLEN/2:XLEN-1])
355 overflow <- ((prod[0:XLEN/2] != [0]*((XLEN/2)+1)) &
356 (prod[0:XLEN/2] != [1]*((XLEN/2)+1)))
358 Special Registers Altered:
363 # Multiply High Word Unsigned
367 * mulhwu RT,RA,RB (Rc=0)
368 * mulhwu. RT,RA,RB (Rc=1)
372 prod[0:XLEN-1] <- (RA)[XLEN/2:XLEN-1] * (RB)[XLEN/2:XLEN-1]
373 RT[XLEN/2:XLEN-1] <- prod[0:(XLEN/2)-1]
374 RT[0:(XLEN/2)-1] <- undefined(prod[0:(XLEN/2)-1])
376 Special Registers Altered:
378 CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
384 * divw RT,RA,RB (OE=0 Rc=0)
385 * divw. RT,RA,RB (OE=0 Rc=1)
386 * divwo RT,RA,RB (OE=1 Rc=0)
387 * divwo. RT,RA,RB (OE=1 Rc=1)
391 dividend[0:(XLEN/2)-1] <- (RA)[XLEN/2:XLEN-1]
392 divisor[0:(XLEN/2)-1] <- (RB) [XLEN/2:XLEN-1]
393 if (((dividend = (0b1 || ([0b0] * ((XLEN/2)-1)))) &
394 (divisor = [1]*(XLEN/2))) |
395 (divisor = [0]*(XLEN/2))) then
396 RT[0:XLEN-1] <- undefined([0]*XLEN)
399 RT[XLEN/2:XLEN-1] <- DIVS(dividend, divisor)
400 RT[0:(XLEN/2)-1] <- undefined([0]*(XLEN/2))
403 Special Registers Altered:
405 CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
408 # Divide Word Unsigned
412 * divwu RT,RA,RB (OE=0 Rc=0)
413 * divwu. RT,RA,RB (OE=0 Rc=1)
414 * divwuo RT,RA,RB (OE=1 Rc=0)
415 * divwuo. RT,RA,RB (OE=1 Rc=1)
419 dividend[0:(XLEN/2)-1] <- (RA)[XLEN/2:XLEN-1]
420 divisor[0:(XLEN/2)-1] <- (RB)[XLEN/2:XLEN-1]
422 RT[XLEN/2:XLEN-1] <- dividend / divisor
423 RT[0:(XLEN/2)-1] <- undefined([0]*(XLEN/2))
426 RT[0:XLEN-1] <- undefined([0]*XLEN)
429 Special Registers Altered:
431 CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
434 # Divide Word Extended
438 * divwe RT,RA,RB (OE=0 Rc=0)
439 * divwe. RT,RA,RB (OE=0 Rc=1)
440 * divweo RT,RA,RB (OE=1 Rc=0)
441 * divweo. RT,RA,RB (OE=1 Rc=1)
445 dividend[0:XLEN-1] <- (RA)[XLEN/2:XLEN-1] || [0]*(XLEN/2)
446 divisor[0:XLEN-1] <- EXTS64((RB)[XLEN/2:XLEN-1])
447 if (((dividend = (0b1 || ([0b0] * (XLEN-1)))) &
448 (divisor = [1]*XLEN)) |
449 (divisor = [0]*XLEN)) then
452 result <- DIVS(dividend, divisor)
453 result_half[0:XLEN-1] <- EXTS64(result[XLEN/2:XLEN-1])
454 if (result_half = result) then
455 RT[XLEN/2:XLEN-1] <- result[XLEN/2:XLEN-1]
456 RT[0:(XLEN/2)-1] <- undefined([0]*(XLEN/2))
461 RT[0:XLEN-1] <- undefined([0]*XLEN)
463 Special Registers Altered:
465 CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
468 # Divide Word Extended Unsigned
472 * divweu RT,RA,RB (OE=0 Rc=0)
473 * divweu. RT,RA,RB (OE=0 Rc=1)
474 * divweuo RT,RA,RB (OE=1 Rc=0)
475 * divweuo. RT,RA,RB (OE=1 Rc=1)
479 dividend[0:XLEN-1] <- (RA)[XLEN/2:XLEN-1] || [0]*(XLEN/2)
480 divisor[0:XLEN-1] <- [0]*(XLEN/2) || (RB)[XLEN/2:XLEN-1]
481 if (divisor = [0]*XLEN) then
484 result <- dividend / divisor
485 if RA[XLEN/2:XLEN-1] <u RB[XLEN/2:XLEN-1] then
486 RT[XLEN/2:XLEN-1] <- result[XLEN/2:XLEN-1]
487 RT[0:(XLEN/2)-1] <- undefined([0]*(XLEN/2))
492 RT[0:XLEN-1] <- undefined([0]*XLEN)
494 Special Registers Altered:
496 CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
507 dividend[0:(XLEN/2)-1] <- (RA)[XLEN/2:XLEN-1]
508 divisor[0:(XLEN/2)-1] <- (RB)[XLEN/2:XLEN-1]
509 if (((dividend = (0b1 || ([0b0] * ((XLEN/2)-1)))) &
510 (divisor = [1]*(XLEN/2))) |
511 (divisor = [0]*(XLEN/2))) then
512 RT[0:XLEN-1] <- undefined([0]*XLEN)
515 RT[0:XLEN-1] <- EXTS64(MODS(dividend, divisor))
516 RT[0:(XLEN/2)-1] <- undefined(RT[0:(XLEN/2)-1])
519 Special Registers Altered:
523 # Modulo Unsigned Word
531 dividend[0:(XLEN/2)-1] <- (RA)[XLEN/2:63]
532 divisor [0:(XLEN/2)-1] <- (RB)[XLEN/2:63]
533 if divisor = [0]*(XLEN/2) then
534 RT[0:XLEN-1] <- undefined([0]*64)
537 RT[XLEN/2:XLEN-1] <- dividend % divisor
538 RT[0:(XLEN/2)-1] <- undefined([0]*(XLEN/2))
541 Special Registers Altered:
545 # Deliver A Random Number
555 Special Registers Altered:
559 # Multiply Low Doubleword
563 * mulld RT,RA,RB (OE=0 Rc=0)
564 * mulld. RT,RA,RB (OE=0 Rc=1)
565 * mulldo RT,RA,RB (OE=1 Rc=0)
566 * mulldo. RT,RA,RB (OE=1 Rc=1)
570 prod[0:(XLEN*2)-1] <- MULS((RA), (RB))
571 RT <- prod[XLEN:(XLEN*2)-1]
572 overflow <- ((prod[0:XLEN] != [0]*(XLEN+1)) &
573 (prod[0:XLEN] != [1]*(XLEN+1)))
575 Special Registers Altered:
580 # Multiply High Doubleword
584 * mulhd RT,RA,RB (Rc=0)
585 * mulhd. RT,RA,RB (Rc=1)
589 prod[0:(XLEN*2)-1] <- MULS((RA), (RB))
592 Special Registers Altered:
596 # Multiply High Doubleword Unsigned
600 * mulhdu RT,RA,RB (Rc=0)
601 * mulhdu. RT,RA,RB (Rc=1)
605 prod[0:(XLEN*2)-1] <- (RA) * (RB)
608 Special Registers Altered:
612 # Multiply-Add High Doubleword VA-Form
620 prod[0:(XLEN*2)-1] <- MULS((RA), (RB))
621 sum[0:(XLEN*2)-1] <- prod + EXTS(RC)[0:XLEN*2]
624 Special Registers Altered:
628 # Multiply-Add High Doubleword Unsigned
632 * maddhdu RT,RA,RB,RC
636 prod[0:(XLEN*2)-1] <- (RA) * (RB)
637 sum[0:(XLEN*2)-1] <- prod + EXTZ(RC)
640 Special Registers Altered:
644 # Multiply-Add Low Doubleword
652 prod[0:(XLEN*2)-1] <- MULS((RA), (RB))
653 sum[0:(XLEN*2)-1] <- prod + EXTS(RC)
654 RT <- sum[XLEN:(XLEN*2)-1]
656 Special Registers Altered:
664 * divd RT,RA,RB (OE=0 Rc=0)
665 * divd. RT,RA,RB (OE=0 Rc=1)
666 * divdo RT,RA,RB (OE=1 Rc=0)
667 * divdo. RT,RA,RB (OE=1 Rc=1)
671 dividend[0:XLEN-1] <- (RA)
672 divisor[0:XLEN-1] <- (RB)
673 if (((dividend = (0b1 || ([0b0] * (XLEN-1)))) &
674 (divisor = [1]*XLEN)) |
675 (divisor = [0]*XLEN)) then
676 RT[0:XLEN-1] <- undefined([0]*XLEN)
679 RT <- DIVS(dividend, divisor)
682 Special Registers Altered:
687 # Divide Doubleword Unsigned
691 * divdu RT,RA,RB (OE=0 Rc=0)
692 * divdu. RT,RA,RB (OE=0 Rc=1)
693 * divduo RT,RA,RB (OE=1 Rc=0)
694 * divduo. RT,RA,RB (OE=1 Rc=1)
698 dividend[0:XLEN-1] <- (RA)
699 divisor[0:XLEN-1] <- (RB)
700 if (divisor = [0]*XLEN) then
701 RT[0:XLEN-1] <- undefined([0]*XLEN)
704 RT <- dividend / divisor
707 Special Registers Altered:
712 # Divide Doubleword Extended
716 * divde RT,RA,RB (OE=0 Rc=0)
717 * divde. RT,RA,RB (OE=0 Rc=1)
718 * divdeo RT,RA,RB (OE=1 Rc=0)
719 * divdeo. RT,RA,RB (OE=1 Rc=1)
723 dividend[0:(XLEN*2)-1] <- (RA) || [0]*XLEN
724 divisor[0:(XLEN*2)-1] <- EXTS128((RB))
725 if (((dividend = (0b1 || ([0b0] * ((XLEN*2)-1)))) &
726 (divisor = [1]*(XLEN*2))) |
727 (divisor = [0]*(XLEN*2))) then
730 result <- DIVS(dividend, divisor)
731 result_half[0:(XLEN*2)-1] <- EXTS128(result[XLEN:(XLEN*2)-1])
732 if (result_half = result) then
733 RT <- result[XLEN:(XLEN*2)-1]
738 RT[0:XLEN-1] <- undefined([0]*XLEN)
740 Special Registers Altered:
745 # Divide Doubleword Extended Unsigned
749 * divdeu RT,RA,RB (OE=0 Rc=0)
750 * divdeu. RT,RA,RB (OE=0 Rc=1)
751 * divdeuo RT,RA,RB (OE=1 Rc=0)
752 * divdeuo. RT,RA,RB (OE=1 Rc=1)
756 dividend[0:(XLEN*2)-1] <- (RA) || [0]*XLEN
757 divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB)
758 if divisor = [0]*(XLEN*2) then
761 result <- dividend / divisor
763 RT <- result[XLEN:(XLEN*2)-1]
768 RT[0:XLEN-1] <- undefined([0]*XLEN)
770 Special Registers Altered:
775 # Modulo Signed Doubleword
785 if (((dividend = (0b1 || ([0b0] * (XLEN-1)))) &
786 (divisor = [1]*XLEN)) |
787 (divisor = [0]*XLEN)) then
788 RT[0:63] <- undefined([0]*XLEN)
791 RT <- MODS(dividend, divisor)
794 Special Registers Altered:
798 # Modulo Unsigned Doubleword
808 if (divisor = [0]*XLEN) then
809 RT[0:XLEN-1] <- undefined([0]*XLEN)
812 RT <- dividend % divisor
815 Special Registers Altered:
819 <!-- Checked March 2021 -->